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malibertymaliberty
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Merge pull request #1098 from The-OpenROAD-Project-staging/secure-large
Secure large
2 parents 632881e + 3b6e289 commit f6ccc16

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11 files changed

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-261
lines changed

11 files changed

+10380
-261
lines changed

‎flow/designs/gf12/bp_dual/config.mk‎

Lines changed: 21 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,23 @@ export DESIGN_NICKNAME = bp_dual
22
export DESIGN_NAME = bsg_chip
33
export PLATFORM = gf12
44

5+
export SYNTH_HIERARCHICAL = 1
6+
#
7+
export RTLMP_FLOW = True
8+
# RTL_MP Settings
9+
export RTLMP_MAX_INST = 30000
10+
export RTLMP_MIN_INST = 10000
11+
export RTLMP_MAX_MACRO = 24
12+
export RTLMP_MIN_MACRO = 4
13+
#
14+
export RTLMP_FENCE_LX ?= 700
15+
export RTLMP_FENCE_LY ?= 700
16+
export RTLMP_FENCE_UX ?= 2450
17+
export RTLMP_FENCE_UY ?= 2300
18+
519
export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.sv2v.v \
620
$(PLATFORM_DIR)/bp/IN12LP_GPIO18_13M9S30P.blackbox.v
21+
export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/yosys/bp_dual_hier_yosys_netlist.v
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823
export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.elab.v.sdc
924

@@ -38,23 +53,19 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
3853
export SEAL_GDS = $(PLATFORM_DIR)/gds/crackstop_3x3.gds
3954

4055

56+
#Package Strategy for pad placement
4157
export FOOTPRINT = $(PLATFORM_DIR)/bp/bsg_bp_dual.package.strategy
4258
export SIG_MAP_FILE = $(PLATFORM_DIR)/bp/soc_bsg_black_parrot.sigmap
4359

4460
export ABC_CLOCK_PERIOD_IN_PS = 1250
4561

46-
export PLACE_DENSITY = 0.20
62+
export TNS_END_PERCENT = 0
63+
export PLACE_DENSITY = 0.55
4764

4865
export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
4966

50-
export PDN_TCL ?= $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
51-
52-
ifneq ($(USE_FILL),)
53-
export DESIGN_TYPE = CHIP
54-
else
55-
export DESIGN_TYPE = CHIP_NODEN
56-
endif
67+
export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
5768

5869
# Define macro halo and channel spacings
59-
export MACRO_PLACE_HALO = 0 0
60-
export MACRO_PLACE_CHANNEL = 30.24 30.24
70+
export MACRO_PLACE_HALO = 7 7
71+
export MACRO_PLACE_CHANNEL = 14 14

‎flow/designs/gf12/bp_dual/config_hier.mk‎

Lines changed: 0 additions & 67 deletions
This file was deleted.

flow/designs/gf12/bp_single/config_hier.mk renamed to flow/designs/gf12/bp_single/config_mpl2.mk

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,11 @@ export RTLMP_MAX_INST = 30000
1010
export RTLMP_MIN_INST = 10000
1111
export RTLMP_MAX_MACRO = 24
1212
export RTLMP_MIN_MACRO = 4
13-
export RTLMP_DEAD_SPACE = 0.10
14-
export RTLMP_KEEPIN = 900 1000 2350 2200
13+
#
14+
export RTLMP_FENCE_LX ?= 900
15+
export RTLMP_FENCE_LY ?= 1300
16+
export RTLMP_FENCE_UX ?= 2350
17+
export RTLMP_FENCE_UY ?= 2500
1518

1619
#netlist
1720
export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/yosys/bp_single_hier_yosys_netlist.v \
@@ -54,21 +57,19 @@ export SEAL_GDS = $(PLATFORM_DIR)/gds/crackstop_3x3.gds
5457
export FOOTPRINT ?= $(PLATFORM_DIR)/bp/bsg_bp_single.package.strategy
5558
export SIG_MAP_FILE = $(PLATFORM_DIR)/bp/soc_bsg_black_parrot.sigmap
5659

57-
# These values must be multiples of placement site
58-
# export DIE_AREA =
59-
# export CORE_AREA =
60-
6160
export ABC_CLOCK_PERIOD_IN_PS = 1250
6261

63-
export PLACE_DENSITY = 0.40
62+
export PLACE_DENSITY = 0.55
63+
export TNS_END_PERCENT = 0
6464

6565
export HAS_IO_CONSTRAINTS = 1
6666
export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
6767

68-
export MACRO_BLOCKAGE_HALO = 25
69-
7068
export PDN_TCL ?= $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
7169

70+
export MACRO_PLACE_HALO = 7 7
71+
export MACRO_PLACE_CHANNEL = 14 14
72+
7273
export DESIGN_TYPE = CHIP
7374

7475
# enable slack margin for setup and hold fix after CTS

‎flow/designs/gf12/ca53/config_mpl2.mk‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
1+
export DESIGN_NAME = ca53_cpu
2+
export PLATFORM = gf12
3+
4+
export FLOW_VARIANT ?= mpl2
5+
6+
export SYNTH_HIERARCHICAL = 1
7+
export RTLMP_FLOW = True
8+
9+
export VERILOG_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
10+
export CACHED_NETLIST = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
11+
12+
export SDC_FILE = $(PLATFORM_DIR)/$(DESIGN_NAME)/sdc/ca53_cpu.sdc
13+
14+
15+
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sc9mcpp84_12lp_base_lvt_c14.lef
16+
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sc9mcpp84_12lp_base_lvt_c14_tt_nominal_max_0p80v_25c.lib
17+
export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sc9mcpp84_12lp_base_lvt_c14.gds2
18+
19+
export WRAP_LEFS = $(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.lef \
20+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1.lef \
21+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1.lef \
22+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1.lef \
23+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1.lef \
24+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1.lef \
25+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1.lef \
26+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1.lef
27+
28+
export WRAP_LIBS = $(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
29+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
30+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
31+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
32+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib \
33+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
34+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
35+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib
36+
37+
38+
39+
export ADDITIONAL_GDS += $(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.gds2 \
40+
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1.gds2 \
41+
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1.gds2 \
42+
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1.gds2 \
43+
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1.gds2 \
44+
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1.gds2 \
45+
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1.gds2 \
46+
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1.gds2
47+
48+
# These values must be multiples of placement site
49+
export DIE_AREA = 0 0 1400 1400
50+
export CORE_AREA = 10 10 1390 1390
51+
52+
export HAS_IO_CONSTRAINTS = 1
53+
export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:1350-1400 -exclude right:* -exclude top:* -exclude bottom:*
54+
55+
export MACRO_PLACE_HALO = 7 7
56+
export MACRO_PLACE_CHANNEL = 14 14
57+
58+
export MACRO_WRAPPERS = $(dir $(DESIGN_CONFIG))/wrappers.tcl
59+
60+
export PLACE_DENSITY_LB_ADDON = 0.05
61+
62+
#export MAX_ROUTING_LAYER = H2
63+
export FASTROUTE_TCL = $(dir $(DESIGN_CONFIG))/fastroute.tcl
64+
#
65+
ifneq ($(USE_FILL),)
66+
export DESIGN_TYPE = CELL
67+
else
68+
export DESIGN_TYPE = CELL_NODEN
69+
endif

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