synthesis: rename CACHED_NETLIST to SYNTH_NETLIST_FILES

and add support for parallel synthesis.

SYNTH_NETLIST_FILES is less mysterious than CACHED_NETLIST.

As far as ORFS is concerned the synthesized netlist files is simply supplied,

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

docs/user/FlowVariables.md

@@ -179,9 +179,11 @@ configuration file.
 | <a name="SKIP_REPORT_METRICS"></a>SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | |
 | <a name="SLEW_MARGIN"></a>SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | |
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| -flatten| |
+| <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | |
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
+| <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | |
 | <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| | |
 | <a name="TAP_CELL_NAME"></a>TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | |
 | <a name="TECH_LEF"></a>TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | |
@@ -208,9 +210,11 @@ configuration file.
 - [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER)
 - [SDC_FILE](#SDC_FILE)
 - [SDC_GUT](#SDC_GUT)
+- [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
 - [SYNTH_GUT](#SYNTH_GUT)
 - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)
 - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
+- [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
 - [VERILOG_FILES](#VERILOG_FILES)

flow/Makefile

@@ -437,7 +437,7 @@ $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
 	mkdir -p $(dir $@)
 	echo $(ABC_CLOCK_PERIOD_IN_PS) > $@
 
-YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
+YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
 
 .PHONY: yosys-dependencies
 yosys-dependencies: $(YOSYS_DEPENDENCIES)

flow/designs/asap7/aes/BUILD.bazel

@@ -0,0 +1,47 @@
+load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_synth")
+
+BLACKBOXES = [
+    "aes_sbox",
+    "aes_key_expand_128",
+    "aes_cipher_top",
+]
+
+[orfs_synth(
+    name = "{name}_netlist_synth".format(name = name),
+    arguments = {
+        "SDC_FILE": "$(location :constraint.sdc)",
+        "SYNTH_BLACKBOXES": " ".join([b for b in BLACKBOXES if b != name]),
+    },
+    data = [":constraint.sdc"],
+    module_top = name,
+    variant = "netlist",
+    verilog_files = ["//designs/src/aes:verilog"],
+) for name in BLACKBOXES]
+
+[filegroup(
+    name = "{name}_netlist".format(name = name),
+    srcs = ["{name}_netlist_synth".format(name = name)],
+    output_group = "1_synth.v",
+) for name in BLACKBOXES]
+
+filegroup(
+    name = "netlists",
+    srcs = [":{}_netlist".format(name) for name in BLACKBOXES],
+)
+
+orfs_flow(
+    name = "aes_cipher_top",
+    arguments = {
+        "ABC_AREA": "1",
+        "CORE_UTILIZATION": "40",
+        "CORE_ASPECT_RATIO": "1",
+        "CORE_MARGIN": "2",
+        "PLACE_DENSITY": "0.65",
+        "TNS_END_PERCENT": "100",
+    },
+    sources = {
+        "SDC_FILE": [":constraint.sdc"],
+        "SYNTH_NETLIST_FILES": [":netlists"],
+    },
+    top = "aes_cipher_top",
+)

flow/designs/asap7/aes/README.md

@@ -0,0 +1,21 @@
+# Parallel synthesis with SYNTH_BLACKBOXES
+
+For large designs, it can be useful to split synthesis for the
+major blocks and combine the synthesized result.
+
+1. Synthesize aes_key_expand_128 module
+
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk LOW_VARIANT=blackbox clean_synth synth
+2. Synthesize top module, which could happen in parallel to 1 but with aes_key_expand_128 blacklisted:
+
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=top clean_synth synth
+3. Combine the synthesis results above:
+
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=combine clean_synth synth
+
+4. View final result:
+
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=combine
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=combine gui_final
+
+![alt text](final.png)

flow/designs/asap7/aes/config.mk

@@ -15,3 +15,17 @@ export PLACE_DENSITY            = 0.65
 export TNS_END_PERCENT          = 100
 export EQUIVALENCE_CHECK       ?=   1
 export REMOVE_CELLS_FOR_EQY     = TAPCELL*
+
+ifeq ($(FLOW_VARIANT),top)
+	export DESIGN_NAME = aes_cipher_top
+	export SYNTH_BLACKBOXES = aes_key_expand_128
+else ifeq ($(FLOW_VARIANT),blackbox)
+	export DESIGN_NAME = aes_key_expand_128
+else ifeq ($(FLOW_VARIANT),combine)
+	export EQUIVALENCE_CHECK = 0
+# List blackbox twice to demonstrates that duplicate modules are ignored.
+	export SYNTH_NETLIST_FILES = \
+	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/top/1_synth.v \
+	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v \
+	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v
+endif

flow/designs/asap7/aes/final.png

@@ -17,7 +17,7 @@ export RTLMP_FENCE_UY ?= 2300
 
 export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.sv2v.v \
                        $(PLATFORM_DIR)/bp/IN12LP_GPIO18_13M9S30P.blackbox.v
-export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/yosys/bp_dual_hier_yosys_netlist.v
+export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/yosys/bp_dual_hier_yosys_netlist.v
 
 export SDC_FILE      = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.elab.v.sdc
 

flow/designs/gf12/bp_dual/config.mk

@@ -5,7 +5,7 @@ export PLATFORM    = gf12
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 1000
 
-export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/yosys/bp_quad_yosys_netlist.v
+export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/yosys/bp_quad_yosys_netlist.v
 export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/rtl/bsg_chip_block.sv2v.v
 
 

flow/designs/gf12/bp_quad/config.mk

@@ -3,7 +3,7 @@ export PLATFORM    = gf12
 
 
 export VERILOG_FILES  = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
-export CACHED_NETLIST = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
+export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
 
 export SDC_FILE      = $(PLATFORM_DIR)/$(DESIGN_NAME)/sdc/ca53_cpu.sdc
 

flow/designs/gf12/ca53/config.mk

@@ -0,0 +1,5 @@
+filegroup(
+    name = "verilog",
+    srcs = glob(include = ["*.v"]),
+    visibility = ["//visibility:public"],
+)