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lines changed Original file line number Diff line number Diff line change 6060 "compare" : " <="
6161 },
6262 "finish__timing__drv__hold_violation_count" : {
63- "value" : 100 ,
63+ "value" : 230 ,
6464 "compare" : " <="
6565 },
6666 "finish__timing__wns_percent_delay" : {
Original file line number Diff line number Diff line change @@ -25,6 +25,16 @@ export SYNTH_HIERARCHICAL = 1
2525
2626export MACRO_PLACE_HALO = 100 100
2727
28+ # We use large placement blockages to try eliminating the channels between
29+ # RAMs in order to make that space inaccessible for GPL. Experiments have
30+ # showed that connections crossing the RAMs vertically can be painful to
31+ # route.
32+ export MACRO_BLOCKAGE_HALO = 151
33+
34+ # There's less space due to the adapted blockage halos, so GPL requires a
35+ # higher density in order to run.
36+ export PLACE_DENSITY = 0.21
37+
2838# CTS tuning
2939export CTS_BUF_DISTANCE = 600
3040export SKIP_GATE_CLONING = 1
Original file line number Diff line number Diff line change 2828 "compare" : " <="
2929 },
3030 "globalroute__antenna_diodes_count" : {
31- "value" : 1185 ,
31+ "value" : 2756 ,
3232 "compare" : " <="
3333 },
3434 "detailedroute__route__wirelength" : {
4040 "compare" : " <="
4141 },
4242 "detailedroute__antenna__violating__nets" : {
43- "value" : 2 ,
43+ "value" : 0 ,
4444 "compare" : " <="
4545 },
4646 "detailedroute__antenna_diodes_count" : {
6060 "compare" : " <="
6161 },
6262 "finish__timing__drv__hold_violation_count" : {
63- "value" : 122 ,
63+ "value" : 101 ,
6464 "compare" : " <="
6565 },
6666 "finish__timing__wns_percent_delay" : {
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