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Rapidus design adjustments for PDK 0.2a
Signed-off-by: Jeff Ng <[email protected]>
1 parent fdb8217 commit f94fc0c

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11 files changed

+163
-19
lines changed

11 files changed

+163
-19
lines changed

‎flow/designs/rapidus2hp/cva6/config.mk‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,17 @@ export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x128m2b1w0c1p0d0
9393
$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
9494
$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib
9595

96-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
96+
97+
DEFAULT_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
98+
_0P2A_6T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_0.2a_6T.sdc
99+
_0P2A_8T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_0.2a_8T.sdc
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101+
# Use $(if) to defer conditional eval until all makefiles are read
102+
export SDC_FILE = $(strip $(if $(filter 0.2a,$(RAPIDUS_PDK_VERSION)), \
103+
$(if $(filter ra02h138_DST_45CPP,$(PLACE_SITE)), \
104+
$(_0P2A_6T_SDC_FILE), \
105+
$(_0P2A_8T_SDC_FILE)), \
106+
$(DEFAULT_SDC_FILE)))
97107

98108
# Must be defined before the ifeq's
99109
export SYNTH_HDL_FRONTEND = slang

‎flow/designs/rapidus2hp/cva6/constraint_0.2a_6T.sdc‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
# Derived from cva6_synth.tcl and Makefiles
2+
3+
source $::env(PLATFORM_DIR)/util.tcl
4+
5+
set clk_name main_clk
6+
set clk_port clk_i
7+
set clk_ports_list [list $clk_port]
8+
set clk_period 820
9+
10+
convert_time_value clk_period
11+
12+
set input_delay [convert_time_value 0.46]
13+
set output_delay [convert_time_value 0.11]
14+
15+
16+
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

‎flow/designs/rapidus2hp/cva6/constraint_0.2a_8T.sdc‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
# Derived from cva6_synth.tcl and Makefiles
2+
3+
source $::env(PLATFORM_DIR)/util.tcl
4+
5+
set clk_name main_clk
6+
set clk_port clk_i
7+
set clk_ports_list [list $clk_port]
8+
set clk_period 600
9+
10+
convert_time_value clk_period
11+
12+
set input_delay [convert_time_value 0.46]
13+
set output_delay [convert_time_value 0.11]
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15+
16+
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

‎flow/designs/rapidus2hp/gcd/config.mk‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,13 @@ ifeq ($(FLOW_VARIANT), verific)
77
endif
88

99
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
10-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
10+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
11+
12+
13+
# Use $(if) to defer conditional eval until all makefiles are read
14+
export CORE_UTILIZATION = $(strip $(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
15+
43, \
16+
45))
1117

12-
export CORE_UTILIZATION = 45
1318
export CORE_MARGIN = .5
1419
export PLACE_DENSITY = 0.42

‎flow/designs/rapidus2hp/hercules_idecode/config.mk‎

Lines changed: 17 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,11 +18,23 @@ export VERILOG_INCLUDE_DIRS = $(SRC_HOME)/hercules_idecode/verilog \
1818
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects.sdc
1919

2020
export SYNTH_HDL_FRONTEND ?= slang
21-
ifeq ($(SYNTH_HDL_FRONTEND), slang)
22-
export CORE_UTILIZATION = 50
23-
else
24-
export CORE_UTILIZATION = 48
25-
endif
21+
22+
# Use $(if) to defer conditional eval until all makefiles are read
23+
#
24+
# | Front End | Place Site | Utilization |
25+
# | --------- | ---------- | ----------- |
26+
# | slang | 6T | 44 |
27+
# | slang | 6T | 50 |
28+
# | verific | 6T | 43 |
29+
# | verific | 6T | 48 |
30+
31+
export CORE_UTILIZATION = $(strip $(if $(filter slang,$(SYNTH_HDL_FRONTEND)), \
32+
$(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
33+
44, \
34+
50), \
35+
$(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
36+
43, \
37+
48)))
2638

2739
export CORE_MARGIN = 1
2840
export PLACE_DENSITY = 0.50

‎flow/designs/rapidus2hp/hercules_is_int/config.mk‎

Lines changed: 16 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -26,15 +26,22 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects
2626
export SYNTH_HDL_FRONTEND ?= slang
2727
export SYNTH_HIERARCHICAL ?= 0
2828

29-
ifeq ($(PLACE_SITE), SC6T)
30-
export CORE_UTILIZATION = 30
31-
else
32-
ifeq ($(SYNTH_HDL_FRONTEND), slang)
33-
export CORE_UTILIZATION = 52
34-
else
35-
export CORE_UTILIZATION = 54
36-
endif
37-
endif
29+
# Use $(if) to defer conditional eval until all makefiles are read
30+
#
31+
# | Front End | Place Site | Utilization |
32+
# | --------- | ---------- | ----------- |
33+
# | slang | 6T | 30 |
34+
# | slang | 6T | 52 |
35+
# | verific | 6T | 30 |
36+
# | verific | 6T | 54 |
37+
38+
export CORE_UTILIZATION = $(strip $(if $(filter slang,$(SYNTH_HDL_FRONTEND)), \
39+
$(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
40+
30, \
41+
52), \
42+
$(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
43+
30, \
44+
54)))
3845

3946
export CORE_MARGIN = 1
4047
export PLACE_DENSITY = 0.58

‎flow/designs/rapidus2hp/ibex/config.mk‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,12 +15,21 @@ export VERILOG_INCLUDE_DIRS = \
1515

1616
export SYNTH_HDL_FRONTEND = slang
1717

18+
1819
# if FLOW_VARIANT == pos_slack, use an SDC file that has a larger clock
1920
# resulting in positive slack
2021
ifeq ($(FLOW_VARIANT),pos_slack)
2122
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_pos_slack.sdc
2223
else
23-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
24+
DEFAULT_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
25+
_0P2A_6T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_0.2a_6T.sdc
26+
_0P2A_8T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_0.2a_8T.sdc
27+
# Use $(if) to defer conditional eval until all makefiles are read
28+
export SDC_FILE = $(strip $(if $(filter 0.2a,$(RAPIDUS_PDK_VERSION)), \
29+
$(if $(filter ra02h138_DST_45CPP,$(PLACE_SITE)), \
30+
$(_0P2A_6T_SDC_FILE), \
31+
$(_0P2A_8T_SDC_FILE)), \
32+
$(DEFAULT_SDC_FILE)))
2433
endif
2534

2635
export CORE_UTILIZATION = 70

‎flow/designs/rapidus2hp/ibex/constraint_0.2a_6T.sdc‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
source $::env(PLATFORM_DIR)/util.tcl
2+
3+
set clk_name core_clock
4+
set clk_port_name clk_i
5+
set clk_period 730
6+
set clk_io_pct 0.2
7+
8+
set clk_port [get_ports $clk_port_name]
9+
10+
convert_time_value clk_period
11+
12+
create_clock -name $clk_name -period $clk_period $clk_port
13+
14+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
15+
16+
set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
17+
$non_clock_inputs
18+
set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
19+
[all_outputs]

‎flow/designs/rapidus2hp/ibex/constraint_0.2a_8T.sdc‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
source $::env(PLATFORM_DIR)/util.tcl
2+
3+
set clk_name core_clock
4+
set clk_port_name clk_i
5+
set clk_period 480
6+
set clk_io_pct 0.2
7+
8+
set clk_port [get_ports $clk_port_name]
9+
10+
convert_time_value clk_period
11+
12+
create_clock -name $clk_name -period $clk_period $clk_port
13+
14+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
15+
16+
set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
17+
$non_clock_inputs
18+
set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
19+
[all_outputs]

‎flow/designs/rapidus2hp/jpeg/config.mk‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,17 @@ endif
99

1010
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
1111
export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
12-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
12+
13+
DEFAULT_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
14+
_0P2A_8T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_0.2a_8T.sdc
15+
# Use $(if) to defer conditional eval until all makefiles are read
16+
export SDC_FILE = $(strip $(if $(filter 0.2a,$(RAPIDUS_PDK_VERSION)), \
17+
$(if $(filter ra02h184_HST_45CPP,$(PLACE_SITE)), \
18+
$(_0P2A_8T_SDC_FILE), \
19+
$(DEFAULT_SDC_FILE)), \
20+
$(DEFAULT_SDC_FILE)))
21+
22+
1323
export ABC_AREA = 1
1424

1525
export CORE_UTILIZATION = 60

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