Skip to content

Commit fa7672b

Browse files
authored
Merge pull request #2918 from Pinata-Consulting/make-run-yosys
makefile: make yosys-run target to explore and report on synthesis results
2 parents 87326a7 + 519ae62 commit fa7672b

File tree

6 files changed

+59
-5
lines changed

6 files changed

+59
-5
lines changed

flow/Makefile

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1026,6 +1026,11 @@ run:
10261026
@mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR)
10271027
($(OPENROAD_CMD) -no_splash $(if $(filter %.py,$(RUN_SCRIPT)),-python) $(RUN_SCRIPT) 2>&1 | tee $(abspath $(LOG_DIR)/$(RUN_LOG_NAME_STEM).log))
10281028

1029+
export RUN_YOSYS_ARGS ?= -c $(SCRIPTS_DIR)/yosys_keep.tcl
1030+
.phony: run-yosys
1031+
run-yosys:
1032+
$(YOSYS_EXE) $(RUN_YOSYS_ARGS)
1033+
10291034
# Utilities
10301035
#-------------------------------------------------------------------------------
10311036
include $(UTILS_DIR)/utils.mk

flow/scripts/README.md

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
# Scripts
2+
3+
Various scripts to support flow as well as utilities.
4+
5+
## make run-yosys
6+
7+
Sets up all the ORFS environment variables and launches Yosys.
8+
9+
Useful to run a Yosys script or interactive mode on the synthesis result to extract information or debug synthesis results using Yosys commands.
10+
11+
Used with the `YOSYS_RUN_ARGS` variable to pass arguments to Yosys. The default arguments is a "Hello world" script that lists all modules with the keep_hierarchy attribute set and writes a report of those modules.
12+
13+
$ make DESIGN_CONFIG=designs/asap7/aes-block/config.mk synth run-yosys
14+
$ cat reports/asap7/aes-block/base/keep.txt
15+
16+
2 modules:
17+
aes_cipher_top aes_key_expand_128
18+
19+
## yosys_load.tcl
20+
21+
Loads in 1_synth.v synthesis result from Yosys. This is useful in automation, such as generating reports from synthesis, but can also be used in interactive inspection.
22+
23+
Example usage to examine results interactively:
24+
25+
make DESIGN_CONFIG=designs/asap7/aes-block/config.mk synth run-yosys RUN_YOSYS_ARGS=-C
26+
27+
Load synthesis result and list modules that were kept in hierarchical synthesis:
28+
29+
[banner deleted]
30+
% source $::env(SCRIPTS_DIR)/yosys_load.tcl
31+
[yosys verbose output deleted]
32+
% ls A:keep_hierarchy=1
33+
34+
2 modules:
35+
aes_cipher_top
36+
aes_key_expand_128
37+
%

flow/scripts/synth_preamble.tcl

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -42,11 +42,7 @@ foreach file $::env(VERILOG_FILES) {
4242
}
4343
}
4444

45-
# Read standard cells and macros as blackbox inputs
46-
# These libs have their dont_use properties set accordingly
47-
read_liberty -overwrite -setattr liberty_cell -lib {*}$::env(DONT_USE_LIBS)
48-
read_liberty -overwrite -setattr liberty_cell \
49-
-unit_delay -wb -ignore_miss_func -ignore_buses {*}$::env(DONT_USE_LIBS)
45+
source $::env(SCRIPTS_DIR)/synth_stdcells.tcl
5046

5147
# Apply toplevel parameters (if exist)
5248
if {[env_var_exists_and_non_empty VERILOG_TOP_PARAMS]} {

flow/scripts/synth_stdcells.tcl

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
# Read standard cells and macros as blackbox inputs
2+
# These libs have their dont_use properties set accordingly
3+
read_liberty -overwrite -setattr liberty_cell -lib {*}$::env(DONT_USE_LIBS)
4+
read_liberty -overwrite -setattr liberty_cell \
5+
-unit_delay -wb -ignore_miss_func -ignore_buses {*}$::env(DONT_USE_LIBS)

flow/scripts/yosys_keep.tcl

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
# Example script, tee list of modules with keep attribute to a
2+
# report file
3+
source $::env(SCRIPTS_DIR)/yosys_load.tcl
4+
5+
tee -o $::env(REPORTS_DIR)/keep.txt ls A:keep_hierarchy=1

flow/scripts/yosys_load.tcl

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
# Load synthesis result
2+
yosys -import
3+
4+
source $::env(SCRIPTS_DIR)/synth_stdcells.tcl
5+
6+
read_verilog $::env(RESULTS_DIR)/1_synth.v

0 commit comments

Comments
 (0)