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Commit fbe6682

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sdc constraints updated
Signed-off-by: vijayank88 <[email protected]>
1 parent 43a21fa commit fbe6682

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3 files changed

+305
-246
lines changed

3 files changed

+305
-246
lines changed
Lines changed: 25 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,29 @@
1-
set clk_name wb_clk_i
2-
set clk_port_name wb_clk_i
3-
set clk_period 960
1+
set top_clk_name wb_clk_i
2+
set clk_period 1500
43
set clk_io_pct 0.2
4+
set clk_port [get_ports $top_clk_name]
5+
create_clock -name $top_clk_name -period $clk_period $clk_port
6+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
7+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
8+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
59

6-
set clk_port [get_ports $clk_port_name]
7-
8-
create_clock -name $clk_name -period $clk_period $clk_port
10+
set tx_clk_name mtx_clk_pad_i
11+
set tx_clk_port [get_ports $tx_clk_name]
12+
set tx_clk_period 500
13+
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
14+
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
15+
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
16+
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
917

10-
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
18+
set rx_clk_name mrx_clk_pad_i
19+
set rx_clk_port [get_ports $rx_clk_name]
20+
set rx_clk_period 500
21+
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
22+
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
23+
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
24+
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
1125

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
26+
set_clock_groups -name core_clock -logically_exclusive \
27+
-group [get_clocks $top_clk_name] \
28+
-group [get_clocks $tx_clk_name] \
29+
-group [get_clocks $rx_clk_name]

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