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Merge pull request #1136 from vijayank88/uart_tcgf180
gf180 uart-blocks test design added
2 parents 568e392 + 6d6b361 commit fc4a4c9

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‎flow/Makefile‎

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# DESIGN_CONFIG=./designs/asap7/jpeg/config.mk
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# DESIGN_CONFIG=./designs/asap7/ethmac/config.mk
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# DESIGN_CONFIG=./designs/asap7/uart/config.mk
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# DESIGN_CONFIG=./designs/asap7/uart-blocks/config.mk
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# DESIGN_CONFIG=./designs/asap7/sha3/config.mk
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# DESIGN_CONFIG=./designs/asap7/riscv32i/config.mk
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# DESIGN_CONFIG=./designs/asap7/swerv_wrapper/config.mk
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# DESIGN_CONFIG=./designs/gf180/jpeg/config.mk
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# DESIGN_CONFIG=./designs/gf180/riscv32i/config.mk
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# DESIGN_CONFIG=./designs/gf180/sha3/config.mk
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# DESIGN_CONFIG=./designs/gf180/uart-blocks/config.mk
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#
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# Default design
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DESIGN_CONFIG ?= ./designs/nangate45/gcd/config.mk

‎flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl‎

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####################################
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# global connections
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####################################
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDP$}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDC$}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VNW$}
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSC$}
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VPW$}
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####################################
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# voltage domains
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####################################
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set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
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####################################
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# standard cell grid
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####################################
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define_pdn_grid -name {block} -voltage_domains {CORE}
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add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins
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add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4}
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add_pdn_stripe -grid {block} -layer {Metal5} -width {4.480} -pitch {89.6} -offset {44.8}
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add_pdn_connect -grid {block} -layers {Metal1 Metal4}
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add_pdn_connect -grid {block} -layers {Metal4 Metal5}
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####################################
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# Block grids
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####################################
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define_pdn_grid -macro -cells uart_rx -halo "2.0 2.0 2.0 2.0" -voltage_domains {CORE} -name BlocksGrid
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add_pdn_connect -grid {BlocksGrid} -layers {Metal4 Metal5}

‎flow/designs/gf180/uart-blocks/config.mk‎

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export PLATFORM = gf180
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export DESIGN_NAME = uart
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export DESIGN_NICKNAME = uart-blocks
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export VERILOG_FILES = ./designs/src/uart-no-param/*.v
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export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export BLOCKS = uart_rx
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export VERILOG_FILES_BLACKBOX = ./designs/src/uart-no-param/uart_rx.v
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export DIE_AREA = 0 0 430 430
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export CORE_AREA = 10 10 420 420
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export HAS_IO_CONSTRAINTS = 1
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export PLACE_PINS_ARGS = -exclude bottom:* -exclude top:* -exclude right:*
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export MACRO_PLACE_HALO = 20 20
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export MACRO_PLACE_CHANNEL = 20 20
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export PDN_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/BLOCKS_grid_strategy.tcl
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export PLACE_DENSITY = 0.60

‎flow/designs/gf180/uart-blocks/constraint.sdc‎

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set clk_name clk
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set clk_port_name clk
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set clk_period 6
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/gf180/uart-blocks/metadata-base-ok.json‎

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}

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