Merge pull request #1075 from The-OpenROAD-Project-staging/secure-mpl2-designs

Secure mpl2 designs

Author: maliberty

flow/designs/asap7/riscv32i/config.mk

@@ -2,23 +2,23 @@ export DESIGN_NICKNAME = riscv32i
 export DESIGN_NAME = riscv_top
 export PLATFORM    = asap7
 
+export SYNTH_HIERARCHICAL = 1
+export RTLMP_FLOW = True
+export MAX_UNGROUP_SIZE ?= 1000
+
 export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
 export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 export ADDITIONAL_LEFS = ./platforms/$(PLATFORM)/lef/fakeram7_256x32.lef
 export ADDITIONAL_LIBS = ./platforms/$(PLATFORM)/lib/fakeram7_256x32.lib
 
-export DIE_AREA = 0 0 120 120
-export CORE_AREA = 5 5 110 110
+export DIE_AREA = 0 0 80 90
+export CORE_AREA = 5 5 75 85 
 
-export PLACE_DENSITY = 0.75
+export PLACE_DENSITY_LB_ADDON = 0.10
 
-export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
-# RTL_MP Settings
-export RTLMP_MAX_INST = 10000
-export RTLMP_MIN_INST = 5000
-export RTLMP_MAX_MACRO = 4
-export RTLMP_MIN_MACRO = 1
 export HAS_IO_CONSTRAINTS = 1
 export PLACE_PINS_ARGS    = -exclude left:* -exclude right:* -exclude top:*
+export MACRO_PLACE_HALO    = 3 3
+export MACRO_PLACE_CHANNEL = 6 6
+#
 export TNS_END_PERCENT   ?= 100

flow/designs/asap7/riscv32i/metadata-base-ok.json

@@ -12,39 +12,39 @@
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 14738,
+        "value": 14366,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__timing__setup__ws": {
-        "value": -359.17,
+        "value": -313.78,
         "compare": ">="
     },
     "cts__timing__setup__ws__pre_repair": {
-        "value": -355.17,
+        "value": -306.3,
         "compare": ">="
     },
     "cts__timing__setup__ws__post_repair": {
-        "value": -355.17,
+        "value": -306.3,
         "compare": ">="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 641,
+        "value": 625,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 641,
+        "value": 625,
         "compare": "<="
     },
     "globalroute__timing__clock__slack": {
-        "value": -47.41,
+        "value": -33.05,
         "compare": ">="
     },
     "globalroute__timing__setup__ws": {
-        "value": -47.41,
+        "value": -33.05,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {

flow/designs/asap7/riscv32i/rules-base.json

@@ -2,15 +2,9 @@ export DESIGN_NAME = ariane
 export PLATFORM    = gf12
 
 export SYNTH_HIERARCHICAL = 1
-export MAX_UNGROUP_SIZE ?= 1000
+export MAX_UNGROUP_SIZE ?= 10000
 export RTLMP_FLOW = True
 #
-# RTL_MP Settings
-export RTLMP_MAX_INST = 20000
-export RTLMP_MIN_INST = 4000
-export RTLMP_MAX_MACRO = 12
-export RTLMP_MIN_MACRO = 4
-export RTLMP_BOUNDARY_WT = 150.0
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \
                        ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v
@@ -24,15 +18,16 @@ export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12lp_1rf_lg8_w64_byte_sspg_sigcmax_0p72
 
 export ADDITIONAL_GDS  = $(PLATFORM_DIR)/gds/gf12lp_1rf_lg8_w64_byte.gds2
 
-export DIE_AREA    = 0 0 750 550
-export CORE_AREA   = 2 2 748 548
-export PLACE_PINS_ARGS = -exclude left:0-250 -exclude left:400-550 -exclude right:* -exclude top:* -exclude bottom:*
+export DIE_AREA    = 0 0 850 600
+export CORE_AREA   = 5 5 745 595
 
-export MACRO_PLACE_HALO = 4 4
-export MACRO_PLACE_CHANNEL = 8 8
+export HAS_IO_CONSTRAINTS = 1
+export PLACE_PINS_ARGS = -exclude left:0-150 -exclude left:450-600 -exclude right:* -exclude top:* -exclude bottom:*
 
-#export PLACE_DENSITY = 0.55
-export PLACE_DENSITY_LB_ADDON = 0.02
+export MACRO_PLACE_HALO = 7 7 
+export MACRO_PLACE_CHANNEL = 14 14
+
+export PLACE_DENSITY_LB_ADDON = 0.05
 
 export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl