1+ {
2+ "constraints__clocks__count" : 1 ,
3+ "constraints__clocks__details" : [
4+ " clk_core: 20.0000"
5+ ],
6+ "cts__clock__skew__hold" : 0.164024 ,
7+ "cts__clock__skew__setup" : 0.164063 ,
8+ "cts__cpu__total" : 4.32 ,
9+ "cts__design__core__area" : 40475.6 ,
10+ "cts__design__die__area" : 1102500.0 ,
11+ "cts__design__instance__area" : 20480.9 ,
12+ "cts__design__instance__area__cover" : 98000 ,
13+ "cts__design__instance__area__macros" : 0 ,
14+ "cts__design__instance__area__padcells" : 424800 ,
15+ "cts__design__instance__area__stdcell" : 20480.9 ,
16+ "cts__design__instance__count" : 1517 ,
17+ "cts__design__instance__count__cover" : 20 ,
18+ "cts__design__instance__count__hold_buffer" : 0 ,
19+ "cts__design__instance__count__macros" : 0 ,
20+ "cts__design__instance__count__padcells" : 48 ,
21+ "cts__design__instance__count__setup_buffer" : 0 ,
22+ "cts__design__instance__count__stdcell" : 1449 ,
23+ "cts__design__instance__displacement__max" : 0 ,
24+ "cts__design__instance__displacement__mean" : 0 ,
25+ "cts__design__instance__displacement__total" : 0 ,
26+ "cts__design__instance__utilization" : 0.506007 ,
27+ "cts__design__instance__utilization__stdcell" : 0.506007 ,
28+ "cts__design__io" : 18 ,
29+ "cts__design__rows" : 52 ,
30+ "cts__design__rows:CoreSite" : 52 ,
31+ "cts__design__sites" : 22308 ,
32+ "cts__design__sites:CoreSite" : 22308 ,
33+ "cts__design__violations" : 0 ,
34+ "cts__flow__errors__count" : 0 ,
35+ "cts__flow__warnings__count" : 0 ,
36+ "cts__mem__peak" : 483980.0 ,
37+ "cts__power__internal__total" : 0.000174158 ,
38+ "cts__power__leakage__total" : 2.46248e-07 ,
39+ "cts__power__switching__total" : 8.0247e-05 ,
40+ "cts__power__total" : 0.000254651 ,
41+ "cts__route__wirelength__estimated" : 37088 ,
42+ "cts__runtime__total" : " 0:04.82" ,
43+ "cts__timing__drv__hold_violation_count" : 0 ,
44+ "cts__timing__drv__max_cap" : 27 ,
45+ "cts__timing__drv__max_cap_limit" : -9.56848 ,
46+ "cts__timing__drv__max_fanout" : 1 ,
47+ "cts__timing__drv__max_fanout_limit" : 8 ,
48+ "cts__timing__drv__max_slew" : 23 ,
49+ "cts__timing__drv__max_slew_limit" : -3.0977 ,
50+ "cts__timing__drv__setup_violation_count" : 0 ,
51+ "cts__timing__setup__tns" : 0 ,
52+ "cts__timing__setup__ws" : 7.12655 ,
53+ "design__io__hpwl" : 0 ,
54+ "design__violations" : 0 ,
55+ "detailedplace__cpu__total" : 1.33 ,
56+ "detailedplace__design__core__area" : 40475.6 ,
57+ "detailedplace__design__die__area" : 1102500.0 ,
58+ "detailedplace__design__instance__area" : 20052.7 ,
59+ "detailedplace__design__instance__area__cover" : 98000 ,
60+ "detailedplace__design__instance__area__macros" : 0 ,
61+ "detailedplace__design__instance__area__padcells" : 424800 ,
62+ "detailedplace__design__instance__area__stdcell" : 20052.7 ,
63+ "detailedplace__design__instance__count" : 1460 ,
64+ "detailedplace__design__instance__count__cover" : 20 ,
65+ "detailedplace__design__instance__count__macros" : 0 ,
66+ "detailedplace__design__instance__count__padcells" : 48 ,
67+ "detailedplace__design__instance__count__stdcell" : 1392 ,
68+ "detailedplace__design__instance__displacement__max" : 12.737 ,
69+ "detailedplace__design__instance__displacement__mean" : 3.356 ,
70+ "detailedplace__design__instance__displacement__total" : 4671.98 ,
71+ "detailedplace__design__instance__utilization" : 0.495428 ,
72+ "detailedplace__design__instance__utilization__stdcell" : 0.495428 ,
73+ "detailedplace__design__io" : 18 ,
74+ "detailedplace__design__rows" : 52 ,
75+ "detailedplace__design__rows:CoreSite" : 52 ,
76+ "detailedplace__design__sites" : 22308 ,
77+ "detailedplace__design__sites:CoreSite" : 22308 ,
78+ "detailedplace__design__violations" : 0 ,
79+ "detailedplace__flow__errors__count" : 0 ,
80+ "detailedplace__flow__warnings__count" : 0 ,
81+ "detailedplace__mem__peak" : 125908.0 ,
82+ "detailedplace__power__internal__total" : 0.000172541 ,
83+ "detailedplace__power__leakage__total" : 2.39199e-07 ,
84+ "detailedplace__power__switching__total" : 7.88849e-05 ,
85+ "detailedplace__power__total" : 0.000251665 ,
86+ "detailedplace__route__wirelength__estimated" : 35850.1 ,
87+ "detailedplace__runtime__total" : " 0:01.43" ,
88+ "detailedplace__timing__drv__hold_violation_count" : 0 ,
89+ "detailedplace__timing__drv__max_cap" : 27 ,
90+ "detailedplace__timing__drv__max_cap_limit" : -9.56848 ,
91+ "detailedplace__timing__drv__max_fanout" : 0 ,
92+ "detailedplace__timing__drv__max_fanout_limit" : 8 ,
93+ "detailedplace__timing__drv__max_slew" : 23 ,
94+ "detailedplace__timing__drv__max_slew_limit" : -3.0977 ,
95+ "detailedplace__timing__drv__setup_violation_count" : 0 ,
96+ "detailedplace__timing__setup__tns" : 0 ,
97+ "detailedplace__timing__setup__ws" : 6.68764 ,
98+ "detailedroute__antenna__violating__nets" : 0 ,
99+ "detailedroute__antenna__violating__pins" : 0 ,
100+ "detailedroute__antenna_diodes_count" : -1 ,
101+ "detailedroute__flow__errors__count" : 0 ,
102+ "detailedroute__flow__warnings__count" : 10 ,
103+ "detailedroute__route__drc_errors" : 0 ,
104+ "detailedroute__route__drc_errors__iter:0" : 784 ,
105+ "detailedroute__route__drc_errors__iter:1" : 431 ,
106+ "detailedroute__route__drc_errors__iter:2" : 432 ,
107+ "detailedroute__route__drc_errors__iter:3" : 77 ,
108+ "detailedroute__route__drc_errors__iter:4" : 17 ,
109+ "detailedroute__route__drc_errors__iter:5" : 0 ,
110+ "detailedroute__route__net" : 1656 ,
111+ "detailedroute__route__net__special" : 22 ,
112+ "detailedroute__route__vias" : 9147 ,
113+ "detailedroute__route__vias__multicut" : 0 ,
114+ "detailedroute__route__vias__singlecut" : 9147 ,
115+ "detailedroute__route__wirelength" : 43262 ,
116+ "detailedroute__route__wirelength__iter:0" : 44006 ,
117+ "detailedroute__route__wirelength__iter:1" : 43510 ,
118+ "detailedroute__route__wirelength__iter:2" : 43478 ,
119+ "detailedroute__route__wirelength__iter:3" : 43298 ,
120+ "detailedroute__route__wirelength__iter:4" : 43261 ,
121+ "detailedroute__route__wirelength__iter:5" : 43262 ,
122+ "finish__clock__skew__hold" : 0.196239 ,
123+ "finish__clock__skew__setup" : 0.195471 ,
124+ "finish__cpu__total" : 4.94 ,
125+ "finish__design__core__area" : 40475.6 ,
126+ "finish__design__die__area" : 1102500.0 ,
127+ "finish__design__instance__area" : 38588.7 ,
128+ "finish__design__instance__area__class:buffer" : 667.699 ,
129+ "finish__design__instance__area__class:clock_buffer" : 384.653 ,
130+ "finish__design__instance__area__class:clock_inverter" : 43.5456 ,
131+ "finish__design__instance__area__class:cover" : 98000 ,
132+ "finish__design__instance__area__class:input_output_pad" : 144000 ,
133+ "finish__design__instance__area__class:input_pad" : 72000 ,
134+ "finish__design__instance__area__class:inverter" : 255.83 ,
135+ "finish__design__instance__area__class:multi_input_combinational_cell" : 9237.11 ,
136+ "finish__design__instance__area__class:output_pad" : 14400 ,
137+ "finish__design__instance__area__class:pad_spacer" : 136800 ,
138+ "finish__design__instance__area__class:power_pad" : 57600 ,
139+ "finish__design__instance__area__class:sequential_cell" : 9434.88 ,
140+ "finish__design__instance__area__class:timing_repair_buffer" : 457.229 ,
141+ "finish__design__instance__area__cover" : 98000 ,
142+ "finish__design__instance__area__macros" : 0 ,
143+ "finish__design__instance__area__padcells" : 424800 ,
144+ "finish__design__instance__area__stdcell" : 38588.7 ,
145+ "finish__design__instance__count" : 3001 ,
146+ "finish__design__instance__count__class:buffer" : 92 ,
147+ "finish__design__instance__count__class:clock_buffer" : 49 ,
148+ "finish__design__instance__count__class:clock_inverter" : 8 ,
149+ "finish__design__instance__count__class:cover" : 20 ,
150+ "finish__design__instance__count__class:input_output_pad" : 10 ,
151+ "finish__design__instance__count__class:input_pad" : 5 ,
152+ "finish__design__instance__count__class:inverter" : 47 ,
153+ "finish__design__instance__count__class:multi_input_combinational_cell" : 990 ,
154+ "finish__design__instance__count__class:output_pad" : 1 ,
155+ "finish__design__instance__count__class:pad_spacer" : 28 ,
156+ "finish__design__instance__count__class:power_pad" : 4 ,
157+ "finish__design__instance__count__class:sequential_cell" : 200 ,
158+ "finish__design__instance__count__class:timing_repair_buffer" : 63 ,
159+ "finish__design__instance__count__cover" : 20 ,
160+ "finish__design__instance__count__macros" : 0 ,
161+ "finish__design__instance__count__padcells" : 48 ,
162+ "finish__design__instance__count__stdcell" : 2933 ,
163+ "finish__design__instance__utilization" : 0.95338 ,
164+ "finish__design__instance__utilization__stdcell" : 0.95338 ,
165+ "finish__design__io" : 18 ,
166+ "finish__design__rows" : 52 ,
167+ "finish__design__rows:CoreSite" : 52 ,
168+ "finish__design__sites" : 22308 ,
169+ "finish__design__sites:CoreSite" : 22308 ,
170+ "finish__design_powergrid__drop__average__net:VDD__corner:default" : 1.19999 ,
171+ "finish__design_powergrid__drop__average__net:VSS__corner:default" : 3.91915e-06 ,
172+ "finish__design_powergrid__drop__worst__net:VDD__corner:default" : 1.53015e-05 ,
173+ "finish__design_powergrid__drop__worst__net:VSS__corner:default" : 1.22197e-05 ,
174+ "finish__design_powergrid__voltage__worst__net:VDD__corner:default" : 1.19998 ,
175+ "finish__design_powergrid__voltage__worst__net:VSS__corner:default" : 1.22197e-05 ,
176+ "finish__flow__errors__count" : 0 ,
177+ "finish__flow__warnings__count" : 0 ,
178+ "finish__mem__peak" : 309360.0 ,
179+ "finish__power__internal__total" : 0.000176823 ,
180+ "finish__power__leakage__total" : 1.36656e-06 ,
181+ "finish__power__switching__total" : 0.000102465 ,
182+ "finish__power__total" : 0.000280654 ,
183+ "finish__runtime__total" : " 0:05.14" ,
184+ "finish__timing__drv__hold_violation_count" : 0 ,
185+ "finish__timing__drv__max_cap" : 27 ,
186+ "finish__timing__drv__max_cap_limit" : -9.56848 ,
187+ "finish__timing__drv__max_fanout" : 1 ,
188+ "finish__timing__drv__max_fanout_limit" : 8 ,
189+ "finish__timing__drv__max_slew" : 23 ,
190+ "finish__timing__drv__max_slew_limit" : -3.0977 ,
191+ "finish__timing__drv__setup_violation_count" : 0 ,
192+ "finish__timing__setup__tns" : 0 ,
193+ "finish__timing__setup__ws" : 6.71916 ,
194+ "finish__timing__wns_percent_delay" : 130.958135 ,
195+ "finish_merge__cpu__total" : 2.11 ,
196+ "finish_merge__mem__peak" : 435324.0 ,
197+ "finish_merge__runtime__total" : " 0:02.69" ,
198+ "floorplan__cpu__total" : 0.74 ,
199+ "floorplan__design__core__area" : 40475.6 ,
200+ "floorplan__design__die__area" : 1102500.0 ,
201+ "floorplan__design__instance__area" : 18381.7 ,
202+ "floorplan__design__instance__area__cover" : 98000 ,
203+ "floorplan__design__instance__area__macros" : 0 ,
204+ "floorplan__design__instance__area__padcells" : 424800 ,
205+ "floorplan__design__instance__area__stdcell" : 18381.7 ,
206+ "floorplan__design__instance__count" : 1199 ,
207+ "floorplan__design__instance__count__cover" : 20 ,
208+ "floorplan__design__instance__count__hold_buffer" : 0 ,
209+ "floorplan__design__instance__count__macros" : 0 ,
210+ "floorplan__design__instance__count__padcells" : 48 ,
211+ "floorplan__design__instance__count__setup_buffer" : 0 ,
212+ "floorplan__design__instance__count__stdcell" : 1131 ,
213+ "floorplan__design__instance__utilization" : 0.454142 ,
214+ "floorplan__design__instance__utilization__stdcell" : 0.454142 ,
215+ "floorplan__design__io" : 0 ,
216+ "floorplan__design__rows" : 52 ,
217+ "floorplan__design__rows:CoreSite" : 52 ,
218+ "floorplan__design__sites" : 22308 ,
219+ "floorplan__design__sites:CoreSite" : 22308 ,
220+ "floorplan__flow__errors__count" : 0 ,
221+ "floorplan__flow__warnings__count" : 5 ,
222+ "floorplan__mem__peak" : 122836.0 ,
223+ "floorplan__power__internal__total" : 0.000174954 ,
224+ "floorplan__power__leakage__total" : 2.25836e-07 ,
225+ "floorplan__power__switching__total" : 7.80393e-05 ,
226+ "floorplan__power__total" : 0.000253219 ,
227+ "floorplan__runtime__total" : " 0:00.84" ,
228+ "floorplan__timing__setup__tns" : 0 ,
229+ "floorplan__timing__setup__ws" : 6.69271 ,
230+ "floorplan_io__cpu__total" : 0.26 ,
231+ "floorplan_io__mem__peak" : 116696.0 ,
232+ "floorplan_io__runtime__total" : " 0:00.37" ,
233+ "floorplan_macro__cpu__total" : 0.27 ,
234+ "floorplan_macro__mem__peak" : 116188.0 ,
235+ "floorplan_macro__runtime__total" : " 0:00.38" ,
236+ "floorplan_pdn__cpu__total" : 0.32 ,
237+ "floorplan_pdn__mem__peak" : 118728.0 ,
238+ "floorplan_pdn__runtime__total" : " 0:00.42" ,
239+ "floorplan_tap__cpu__total" : 0.26 ,
240+ "floorplan_tap__mem__peak" : 114648.0 ,
241+ "floorplan_tap__runtime__total" : " 0:00.35" ,
242+ "flow__errors__count" : 0 ,
243+ "flow__warnings__count" : 0 ,
244+ "globalplace__cpu__total" : 62.36 ,
245+ "globalplace__design__core__area" : 40475.6 ,
246+ "globalplace__design__die__area" : 1102500.0 ,
247+ "globalplace__design__instance__area" : 18615.7 ,
248+ "globalplace__design__instance__area__cover" : 98000 ,
249+ "globalplace__design__instance__area__macros" : 0 ,
250+ "globalplace__design__instance__area__padcells" : 424800 ,
251+ "globalplace__design__instance__area__stdcell" : 18615.7 ,
252+ "globalplace__design__instance__count" : 1262 ,
253+ "globalplace__design__instance__count__cover" : 20 ,
254+ "globalplace__design__instance__count__macros" : 0 ,
255+ "globalplace__design__instance__count__padcells" : 48 ,
256+ "globalplace__design__instance__count__stdcell" : 1194 ,
257+ "globalplace__design__instance__utilization" : 0.459925 ,
258+ "globalplace__design__instance__utilization__stdcell" : 0.459925 ,
259+ "globalplace__design__io" : 18 ,
260+ "globalplace__design__rows" : 52 ,
261+ "globalplace__design__rows:CoreSite" : 52 ,
262+ "globalplace__design__sites" : 22308 ,
263+ "globalplace__design__sites:CoreSite" : 22308 ,
264+ "globalplace__flow__errors__count" : 0 ,
265+ "globalplace__flow__warnings__count" : 0 ,
266+ "globalplace__mem__peak" : 454168.0 ,
267+ "globalplace__power__internal__total" : 0.000172473 ,
268+ "globalplace__power__leakage__total" : 2.27703e-07 ,
269+ "globalplace__power__switching__total" : 7.85438e-05 ,
270+ "globalplace__power__total" : 0.000251244 ,
271+ "globalplace__runtime__total" : " 0:04.08" ,
272+ "globalplace__timing__setup__tns" : 0 ,
273+ "globalplace__timing__setup__ws" : 6.6878 ,
274+ "globalplace_io__cpu__total" : 0.26 ,
275+ "globalplace_io__mem__peak" : 116700.0 ,
276+ "globalplace_io__runtime__total" : " 0:00.35" ,
277+ "globalplace_skip_io__cpu__total" : 51.82 ,
278+ "globalplace_skip_io__mem__peak" : 120792.0 ,
279+ "globalplace_skip_io__runtime__total" : " 0:01.19" ,
280+ "globalroute__antenna__violating__nets" : 0 ,
281+ "globalroute__antenna__violating__pins" : 0 ,
282+ "globalroute__antenna_diodes_count" : 0 ,
283+ "globalroute__clock__skew__hold" : 0.179886 ,
284+ "globalroute__clock__skew__setup" : 0.181834 ,
285+ "globalroute__cpu__total" : 12.16 ,
286+ "globalroute__design__core__area" : 40475.6 ,
287+ "globalroute__design__die__area" : 1102500.0 ,
288+ "globalroute__design__instance__area" : 20480.9 ,
289+ "globalroute__design__instance__area__cover" : 98000 ,
290+ "globalroute__design__instance__area__macros" : 0 ,
291+ "globalroute__design__instance__area__padcells" : 424800 ,
292+ "globalroute__design__instance__area__stdcell" : 20480.9 ,
293+ "globalroute__design__instance__count" : 1517 ,
294+ "globalroute__design__instance__count__cover" : 20 ,
295+ "globalroute__design__instance__count__hold_buffer" : 0 ,
296+ "globalroute__design__instance__count__macros" : 0 ,
297+ "globalroute__design__instance__count__padcells" : 48 ,
298+ "globalroute__design__instance__count__setup_buffer" : 0 ,
299+ "globalroute__design__instance__count__stdcell" : 1449 ,
300+ "globalroute__design__instance__displacement__max" : 0 ,
301+ "globalroute__design__instance__displacement__mean" : 0 ,
302+ "globalroute__design__instance__displacement__total" : 0 ,
303+ "globalroute__design__instance__utilization" : 0.506007 ,
304+ "globalroute__design__instance__utilization__stdcell" : 0.506007 ,
305+ "globalroute__design__io" : 18 ,
306+ "globalroute__design__rows" : 52 ,
307+ "globalroute__design__rows:CoreSite" : 52 ,
308+ "globalroute__design__sites" : 22308 ,
309+ "globalroute__design__sites:CoreSite" : 22308 ,
310+ "globalroute__design__violations" : 0 ,
311+ "globalroute__flow__errors__count" : 0 ,
312+ "globalroute__flow__warnings__count" : 0 ,
313+ "globalroute__mem__peak" : 469788.0 ,
314+ "globalroute__power__internal__total" : 0.000175714 ,
315+ "globalroute__power__leakage__total" : 2.46248e-07 ,
316+ "globalroute__power__switching__total" : 9.47342e-05 ,
317+ "globalroute__power__total" : 0.000270695 ,
318+ "globalroute__route__wirelength__estimated" : 37088 ,
319+ "globalroute__runtime__total" : " 0:02.34" ,
320+ "globalroute__timing__clock__slack" : 6.832 ,
321+ "globalroute__timing__drv__hold_violation_count" : 0 ,
322+ "globalroute__timing__drv__max_cap" : 27 ,
323+ "globalroute__timing__drv__max_cap_limit" : -9.56848 ,
324+ "globalroute__timing__drv__max_fanout" : 1 ,
325+ "globalroute__timing__drv__max_fanout_limit" : 8 ,
326+ "globalroute__timing__drv__max_slew" : 23 ,
327+ "globalroute__timing__drv__max_slew_limit" : -3.0977 ,
328+ "globalroute__timing__drv__setup_violation_count" : 0 ,
329+ "globalroute__timing__setup__tns" : 0 ,
330+ "globalroute__timing__setup__ws" : 6.83167 ,
331+ "placeopt__cpu__total" : 1.17 ,
332+ "placeopt__design__core__area" : 40475.6 ,
333+ "placeopt__design__die__area" : 1102500.0 ,
334+ "placeopt__design__instance__area" : 20052.7 ,
335+ "placeopt__design__instance__area__cover" : 98000 ,
336+ "placeopt__design__instance__area__macros" : 0 ,
337+ "placeopt__design__instance__area__padcells" : 424800 ,
338+ "placeopt__design__instance__area__stdcell" : 20052.7 ,
339+ "placeopt__design__instance__count" : 1460 ,
340+ "placeopt__design__instance__count__cover" : 20 ,
341+ "placeopt__design__instance__count__macros" : 0 ,
342+ "placeopt__design__instance__count__padcells" : 48 ,
343+ "placeopt__design__instance__count__stdcell" : 1392 ,
344+ "placeopt__design__instance__utilization" : 0.495428 ,
345+ "placeopt__design__instance__utilization__stdcell" : 0.495428 ,
346+ "placeopt__design__io" : 18 ,
347+ "placeopt__design__rows" : 52 ,
348+ "placeopt__design__rows:CoreSite" : 52 ,
349+ "placeopt__design__sites" : 22308 ,
350+ "placeopt__design__sites:CoreSite" : 22308 ,
351+ "placeopt__flow__errors__count" : 0 ,
352+ "placeopt__flow__warnings__count" : 1 ,
353+ "placeopt__mem__peak" : 388660.0 ,
354+ "placeopt__power__internal__total" : 0.000172473 ,
355+ "placeopt__power__leakage__total" : 2.39199e-07 ,
356+ "placeopt__power__switching__total" : 7.85438e-05 ,
357+ "placeopt__power__total" : 0.000251256 ,
358+ "placeopt__runtime__total" : " 0:01.52" ,
359+ "placeopt__timing__drv__floating__nets" : 2 ,
360+ "placeopt__timing__drv__floating__pins" : 0 ,
361+ "placeopt__timing__drv__hold_violation_count" : 0 ,
362+ "placeopt__timing__drv__max_cap" : 27 ,
363+ "placeopt__timing__drv__max_cap_limit" : -9.56848 ,
364+ "placeopt__timing__drv__max_fanout" : 0 ,
365+ "placeopt__timing__drv__max_fanout_limit" : 8 ,
366+ "placeopt__timing__drv__max_slew" : 23 ,
367+ "placeopt__timing__drv__max_slew_limit" : -3.0977 ,
368+ "placeopt__timing__drv__setup_violation_count" : 0 ,
369+ "placeopt__timing__setup__tns" : 0 ,
370+ "placeopt__timing__setup__ws" : 6.68781 ,
371+ "run__flow__design" : " i2c-gpio-expander" ,
372+ "run__flow__generate_date" : " 2025-01-21 05:56" ,
373+ "run__flow__metrics_version" : " Metrics_2.1.2" ,
374+ "run__flow__openroad_commit" : " N/A" ,
375+ "run__flow__openroad_version" : " v2.0-18407-g2978ae66e" ,
376+ "run__flow__platform" : " ihp-sg13g2" ,
377+ "run__flow__platform__capacitance_units" : " 1pF" ,
378+ "run__flow__platform__current_units" : " 1uA" ,
379+ "run__flow__platform__distance_units" : " 1um" ,
380+ "run__flow__platform__power_units" : " 1pW" ,
381+ "run__flow__platform__resistance_units" : " 1kohm" ,
382+ "run__flow__platform__time_units" : " 1ns" ,
383+ "run__flow__platform__voltage_units" : " 1v" ,
384+ "run__flow__platform_commit" : " a59f17e04d9776fa9c2bd22acce6d8cdadbbfad2" ,
385+ "run__flow__scripts_commit" : " a59f17e04d9776fa9c2bd22acce6d8cdadbbfad2" ,
386+ "run__flow__uuid" : " b70aab41-2441-4e19-ae9b-31b892e1c8bd" ,
387+ "run__flow__variant" : " base" ,
388+ "synth__cpu__total" : 2.82 ,
389+ "synth__design__instance__area__stdcell" : 248780.25 ,
390+ "synth__design__instance__count__stdcell" : 1147.0 ,
391+ "synth__mem__peak" : 36648.0 ,
392+ "synth__runtime__total" : " 0:02.93" ,
393+ "total_time" : " 0:00:28.850000"
394+ }
0 commit comments