Disable insertion delay for gf12/bp_single cts

This works around ~1000 ps clock tree skew introduced by inserting
105 delay buffers in front of the `bp_clk` register tree.

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

flow/designs/gf12/bp_single/config.mk

@@ -66,5 +66,7 @@ else
 export DESIGN_TYPE = CHIP_NODEN
 endif
 
+export CTS_ARGS = -no_insertion_delay
+
 # enable slack margin for setup and hold fix after CTS
 export SETUP_SLACK_MARGIN ?= 100