Issue with Yosys on synthesis

[lustefan97]

Hello,

I have a design that I am trying to synthesize but I have an issue with the synthesis step in the automatic flow and Yosys GitHub page seems not very active, so I am taking a shot here.
Essentially I am trying to synthesize a large fully connected LDPC module, but I have the following error message that stop Yosys :

10.23.1. Executing OPT_EXPR pass (perform const folding).
10.23.2. Executing OPT_MERGE pass (detect identical cells).
terminate called after throwing an instance of 'std::length_error'
what():  hash table exceeded maximum size. use a ILP64 abi for larger tables.
Command terminated by signal 6
Elapsed time: 1:23:25[h:]min:sec. CPU time: user 4880.99 sys 106.84 (99%). Peak memory: 34150252KB. 

I am wondering if anyone has any idea of what could be wrong/has encountered this issue

[maliberty]

It is better to ask in https://github.com/YosysHQ/yosys or their slack channel. Note also The-OpenROAD-Project/OpenROAD#2106

[lustefan97]

Will check it out, sorry for the inconvenience !