Changes from V2.0-18737 to V2.0-23724 throws an error

[pars97]

I bought a new machine that I want to run the OpenROAD flow onto.
Previously working flow on my laptop (V2.0-18373) was going through all my design (quite slowly but still) and outputted me a GDS file.

On the new machine, (V2.0-23724), I get an error that I do not recognize, related to yosys :

Using ABC speed script.
Extracting clock period from SDC file: ./results/amf/CORE_2501PH/base/clock_period.txt   
Setting clock period to 100
1. Executing RTLIL frontend.
2. Executing HIERARCHY pass (managing design hierarchy).
2.1. Analyzing design hierarchy..
2.2. Analyzing design hierarchy..
3. Executing PROC pass (convert processes to netlists).
3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
3.4. Executing PROC_INIT pass (extract init attributes).
3.5. Executing PROC_ARST pass (detect async resets in processes).
3.6. Executing PROC_ROM pass (convert switches to ROMs).
3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
3.9. Executing PROC_DFF pass (convert process syncs to FFs).
3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
3.12. Executing OPT_EXPR pass (perform const folding).
ERROR: No such module: \1
ERROR: TCL interpreter returned an error: Yosys command produced an error
Command exited with non-zero status 1

This error is only appearing when I try my own platform and own designs. When I do testing with the gf180 or the nand45, the flow works well.

My hunch is that changes were made with the addition of the slang of yosys, although cannot confirm it.

At step 3, I added a yosys proc because my design requires it [https://github.com//discussions/3170].

Do you have insights on how to run it? I can still do the flow on my older laptop if needed but would really like to get the new PC up to this task.

[pars97]

While debugging, I found the problem in my design files (unsuprisingly - code 18, where the error factor is 18 inches away from the screen - is always a good choice to look at first).

For future users that have the same problem; in my config.mk file of my design, i had the following line :

export SYNTH_KEEP_MODULES = 1

Which I thought was about keeping the module with a True/False flag. This flag was unused in V2.0-18737 but is used in V2.0-23724 and, is not a flag at all!

Instead, replace it with something like this:

export SYNTH_KEEP_MODULES = submodule1 submodule2 submodule3

Where submodule1 is the name of the module in your verilog file that is not your top module.

Cheers,