Script breaks down on eFPGA+ibex Design

[nichkara]

Like said in the title, I am trying to use ORFS with a rather big design.

I currently run my script on a server with 1/2 TB RAM and ~250GB free memory.

My problem is, that ORFS still seems to resource hungry resulting in stopping the docker container.

Any ideas on how to do only the bare minimum? I don't need logs etc. as it is a resource problem and worked with smaller designs.

[maliberty]

How many placeable objects in the design? Logs don't consume memory. What step are you at in the flow when it fails? Could you run the design hierarchically?

[nichkara]

Logs consume Memory on the hard drive (Well over 100GB yosys log). I managed to get it through the synthesis step.

Running the design hierarchically would not be possible without major refactoring which I honestly don't know how to do.

[Edit] The flow crashes during the floorplanning step as it seems:

fig_dffesr.LUT_flop$_DFFE_PP_/D
      980 |       0 |     971 |        1 |      0 |     7 |    +0.1% | -4845.881 | -3059817.2 |   2647 | ciu_i.efpga_ciu.eFPGA_inst.Tile_X3Y2_LUT4AB.Inst_LA_LUT4c_frame_config_dffesr.LUT_flop$_DFFE_PP_/D
      990 |       0 |     981 |        1 |      0 |     7 |    +0.1% | -4845.115 | -3059314.8 |   2647 | ciu_i.efpga_ciu.eFPGA_inst.Tile_X3Y2_LUT4AB.Inst_LA_LUT4c_frame_config_dffesr.LUT_flop$_DFFE_PP_/D
Command terminated by signal 9
Elapsed time: 2:23:18[h:]min:sec. CPU time: user 9014.00 sys 17459.83 (307%). Peak memory: 493102124KB.
make[1]: *** [Makefile:422: do-2_1_floorplan] Error 1
make: *** [Makefile:422: results/ihp-sg13g2/riscvar/base/2_1_floorplan.odb] Error 2

The program does run out of RAM, how can that demand be reduced?

[Edit 2] number instances in verilog is 286645

[maliberty]

100GB yosys log sounds like something has gone terribly wrong. In any case it wouldn't cause you to run out of RAM. 286645 is not that many instances and should easily run on the machine you describe ( wouldn't even call it a particularly big design). I really have no idea what is wrong and without a test case can't guess.

[nichkara]

It turned out, that my FPGA design is stuck in a logic loop, so nothing related to openroad.

Sorry for bothering.