Running CTS twice?

[paolopedroso]

I'm implementing two-phase clocking and at a part by running CTS sequentially for each clock in separate stages (4_1_cts for clk_1, 4_2_cts for clk_2). The first stage succeeds, but the second stage fails with a segfault.
Makefile:
// CTS step
$(eval $(call do-step,4_1_cts,$(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/3_place.sdc,cts_clk_1))
$(eval $(call do-step,4_2_cts,$(RESULTS_DIR)/4_1_cts.odb $(RESULTS_DIR)/4_1_cts.sdc,cts_clk_2))

cts_clk_1.tcl (Works):
tclload_design 3_place.odb 3_place.sdc
repair_clock_inverters

set cts_args [list
-sink_clustering_enable
-balance_levels
-repair_clock_nets
-clk_nets clk_1]

log_cmd clock_tree_synthesis {*}$cts_args
detailed_placement
estimate_parasitics -placement

write_db $::env(RESULTS_DIR)/4_1_cts.odb
write_sdc -no_timestamp $::env(RESULTS_DIR)/4_1_cts.sdc

---

cts_clk_2.tcl (Segfaults):
tclload_design 4_1_cts.odb 4_1_cts.sdc # Loads design with clk_1 tree already built

set cts_args [list
-sink_clustering_enable
-balance_levels
-repair_clock_nets
-clk_nets clk_2]

log_cmd clock_tree_synthesis {*}$cts_args # Segfaults here

I want to run clock_tree_synthesis separately for each clock domain (clk_1 and clk_2) with independent parameters and configurations. What is the recommended approach?

[maliberty]

This isn't a question??

[paolopedroso]

Sorry mis clicked. Here's my full question.

[maliberty]

Can you make a test case that shows the problem? I think you have the right concept in your scripts

[paolopedroso]

test_case.zip

• test_case_makefile.mk contains CTS step, so replace ORFS CTS with contents of test_case_makefile.mk.
• test_case_gcd.v is a synthesized Verilog netlist of the gcd design that has been generated by Yosys using a two-phase clocking scheme.
• *.tcl is my way of creating two independent clock trees finishing with checks.
  run with make DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk to output segfault.

[paolopedroso]

test_case.zip

That one is empty, files should be in test_case/test_case. My mistake.