Significant area reduction using abc during canonicalize

[lo7ev]

Adding synth -flatten; abc into the synth_canonicalize.tcl after hierarchy check and before writing actual rtlil leads to 35% reduction of area after the floorplaning stage on various designs. Is this a mistake or a feature?

[maliberty]

@povik thoughts?

[povik]

@lo7ev can this be reproduced with any of ORFS designs?

[lo7ev]

I tried to synthesize simple circuits (Add two 8bit numbers or multiply them) with asap7 library