Sky130 PDK Flow Integration Docs

[evanvnguyen]

I've been getting into the open source EDA ecosystem and am interested in learning more about design integration guidelines. I have the sky130 std cells and design collateral on hand, but the Sky130 PDK documentation on their site seems lackluster.

I'm wondering if there are any chip-integration guidelines docs or flows designed specifically for sky130 foundry. I noticed many people have TO'd with TinyTapeout or efabless. TT has a GitHub actions pipeline that uses LibreLane. Is LibreLane / openroad PDK agnostic? This is my main point of confusion. For pure digital designs, some foundries have integration docs akin to the following and tailor their flow towards them.

APR block design concepts
STD-cell region (core-area) guidelines
Routing blockage layers
ESD clamp usage
Top-level integration rules
Pin track alignment
Power ring guidelines
Metal layer design rules (Mx/My)
ESD/latch-up prevention
PG antenna rules
Dummy fill requirements

I'm unclear if OpenROAD/LibreLane are truly PDK-agnostic or if Sky130/GF180/IHP130 have foundry-specific integration docs not published in standard repositories. I prefer scripting my own flow rather than using TT's actions flow and LibreLane's python environment.

Let me know if I'm missing something, thanks!