Add coralnpu on asap7

[maliberty]

Description

Add https://github.com/google-coral/coralnpu to ORFS on asap7

Suggested Solution

Use fakeram as needed.

Additional Context

No response

[jeffng-or]

From Peter Gadfort:

first pass, yosys gets stuck in a techmapping pass, so will require some debugging to figure out why

I'll share something later today, but it's before the PDK is even referenced, so I don't think that would matter (it's something in the RTL from the Chisel subsystem)

test case: https://drive.google.com/file/d/1Glx6R5E9fm3ldPyH_hJKmE0mLV123_we/view?usp=sharing

[oharboe]

How about adding a PR for coralnpu with bazel-orfs?

[maliberty]

In ORFS? We have no bazel-orfs test there.

[jeffng-or]

@gadfort , which steps did you follow to generate the SV with the CoralNPUChiselSubsystem top module?

I was looking at the Integration Guide and it gives instructions on how to generate the SV for top modules with the names CoreMiniAxi or RvvCoreMiniAxi.

[gadfort]

The issue with yosys stems from the Chisel generated code, so once I isolated that thats the only file included. It was generated by building just the chisel part isolation, not sure if something went wrong when I ran it, but yosys still chokes on it.

I was following some of the FPGA integration since it has a top level with a reasonable number of ports (ie. integrated external memory).

[oharboe]

FYI, Chisel allows a lot of control over how code is generated via firtool, such as memories, verilog style, disabling verification layers, disable randomization of registers, etc. This used to be more important before slang as yosys without slang is much more finicky about what Verilog constructs that it supports.

[maliberty]

Note that slang is not yet on by default

[oharboe]

Note that slang is not yet on by default

Should it ever be?

It is easily enabled per project...

[maliberty]

I don't see why not as the sv support in yosys is inferior.

[oharboe]

I don't see why not as the sv support in yosys is inferior.

Noted. Timeframe to make slang default? "asymptotic goal"?

[maliberty]

More just a matter of getting around to testing it and making sure nothing breaks.

[jeffng-or]

The issue with yosys stems from the Chisel generated code, so once I isolated that thats the only file included. It was generated by building just the chisel part isolation, not sure if something went wrong when I ran it, but yosys still chokes on it.

I was following some of the FPGA integration since it has a top level with a reasonable number of ports (ie. integrated external memory).

Thanks for the clarification. I wasn't looking at the FPGA code before. I'm able to export essentially the same SV as you included in your tarball (only changes appeared to be the ifdef's and some newlines).

So, now the question is what version of the design should be added to ORFS:

1. CoralNPUChiselSubsystem (FPGA)
2. CoreMiniAxi (scalar-only Coral NPU configuration is provided that can integrate with an AXI-based system)
3. RvvCoreMiniAxi (RISC-V vector (RV32IMF_Zve32x) version of Coral NPU)

[oharboe]

@maliberty Perhaps it is a bridge too far to try to fake RAM for this design in asap7 initially?

There's interesting stuff to be learned from this design, other than how to set up SRAMs?

Given that the SRAMs will have a mismatch in behavioral model (number of ports, read clock, etc.), wrapper/interfaced logic would have to be written to combine one or more fake RAMs to a single RAM. This is what barstools does in Chipyard and SRAM inference support in FPGA.

I find that setting number of rows in SRAMs to 1 row and then looking at what else there is to learn from a big design first is a good first step.

Realism in SRAM is dessert...

[oharboe]

W.r.t. interesting issues to investigate with coralnpu, I think memory instantiation and placement is the least novel/interestin, there are already designs that investigate that.

It would be neat with a feature that could put a pin in memory instantiation and placement to look for other interesting aspects with coralnpu:

#3621