[slang] Support a way to map from non-mangled presynthesis name to mangled post synthesis name

[oharboe]

Description

Is there a way to disable the name mangling to be compatible with Yosys?

Of course there are cases when names need to be individualized due to parameters, but for my use-case there's no SystemVerilog parameterization, so there's no ambiguity.

slang mangles module names during synthesis.

Original name Foo_3 mangled name Foo_3$SomeTop.bar.foo.

This is the code that's broken: original_name is no longer pre-synthesis, but mangled slang name.

set mapping {}
set block [ord::get_db_block]
foreach module [$block getModules] {
  set prop [odb::dbStringProperty_find $module "original_name"]
  if { $prop != "NULL" } {
	set module_name [$module getName]
	set original_name [$prop getValue]
    if {[catch {dict get $mapping $original_name} current]} {
        set current {}
    } else {
        set current [dict get $mapping $original_name]
    }
    lappend current $module_name
    dict set mapping $original_name $current
  } else {
    dict set mapping [$module getName] {}
  }
}

Suggested Solution

How to disable this mangling? Alternatively write out a reports/ file with a map.

Additional Context

No response

[povik]

Is there a way to disable the name mangling to be compatible with Yosys?

There isn't at the moment. In the future slang will have an alternative naming scheme (povik/yosys-slang#103) which should stop renaming modules unless there are parameters or other reasons.

I think a good solution is to rely on a "hdlname" attribute with the pre-synthesis name. This would work in the face of parametrization too. We need to (1) attach hdlname to modules in slang (2) adjust the verilog reader in openroad to pick up this attribute.