[ERROR] asap7-ibex write_verilog produces syntax error verilog with OPENROAD_HIERARCHICAL enabled

[liW-J]

Subject

[Stage]: Other. Please describe below.

Describe the bug

when running the default asap7-ibex flow with ORFS, the generated 6_final.v cannot be correctly parsed by OpenROAD due to invalid Verilog syntax. This issue seems to be related to the recently introduced default enablement of OPENROAD_HIERARCHICAL for some designs.

openroad> read_verilog ./results/asap7/ibex/base/6_final.v
[ERROR STA-0164] ./results/asap7/ibex/base/6_final.v line 72893, syntax error
STA-0164
while evaluating read_verilog ./results/asap7/ibex/base/6_final.v

Expected Behavior

The verilog generated by write_verilog should be syntactically valid and readable by OpenROAD.

I tested nangate45-aes, with OPENROAD_HIERARCHICAL also default enabled. Its generated 6_final.v can be successfully parsed using read_verilog:

openroad> read_verilog ./results/nangate45/aes/base/6_final.v
openroad> 

For asap7-ibex, we tried using yosys to flatten the verilog output during the synthesis stage, and the final verilog written by OpenROAD can be read correctly.

Environment

ORFS git commit: e19b7a5176e45bae645ba2d5b46f4457e8913b1c
OpenROAD git commit: 36764173fae6bb1eb4b35f0c2138f42b3cdfadd8
kernel: Linux 3.10.0-1160.el7.x86_64
os: Ubuntu 24.04.3 LTS (Noble Numbat)
cmake version 3.28.3
-- The CXX compiler identification is GNU 13.3.0
-- Detecting CXX compiler ABI info
-- Detecting CXX compiler ABI info - done
-- Check for working CXX compiler: /usr/bin/c++ - skipped
-- Detecting CXX compile features
-- Detecting CXX compile features - done
-- OpenROAD version: v2.0-27957-g36764173fa
-- System name: Linux
-- Compiler: GNU 13.3.0
-- Build type: RELEASE
-- Install prefix: /usr/local
-- C++ Standard: 20
-- C++ Standard Required: ON
-- C++ Extensions: OFF
-- LTO/IPO is disabled
-- The C compiler identification is GNU 13.3.0
-- Detecting C compiler ABI info
-- Detecting C compiler ABI info - done
-- Check for working C compiler: /usr/bin/cc - skipped
-- Detecting C compile features
-- Detecting C compile features - done

To Reproduce

Run the default ORFS flow for asap7-ibex, and the flow completes successfully.

The generated verilog file has following issues casued syntax error:

• The net named net (wire net;) is declared multiple times in the top-level module, at line 70 and line 20117;
• ome port connections contain invalid escaped identifiers, for example at line 72893: .Y[32:1]({net1853,

Here is the 6_final.v of asap7-ibex witten by ORFS: https://gist.github.com/liW-J/0ffea3db98922f26830b3f59dbb29a3a

Relevant log output

lwjiang@hnode33:/OpenROAD-flow-scripts/flow$ openroad
OpenROAD v2.0-27957-g36764173fa 
Features included (+) or not (-): +GPU +GUI +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
openroad> read_verilog ./results/asap7/ibex/base/6_final.v
[ERROR STA-0164] ./results/asap7/ibex/base/6_final.v line 72893, syntax error
STA-0164
while evaluating read_verilog ./results/asap7/ibex/base/6_final.v
openroad>

Screenshots

No response

Additional Context

No response

[jhkim-pii]

Thank you for the reporting. I reproduced the issue.

Issue 1 - .Y\[32:1\]

Yosys generated the following module and it uses \Y[32:1] as a port name.

  1430 module \ALU_33_0_33_0_33_unused_CO_X_Y[0]_HAN_CARLSON (A, B, BI, CI, \Y[32:1] );
  1431   input [32:0] A;
  1432   wire [32:0] A;
  1433   input [32:0] B;
  1434   wire [32:0] B;
  1435   input BI;
  1436   wire BI;
  1437   input CI;
  1438   wire CI;
  1439   output [31:0] \Y[32:1] ;
  1440   wire [31:0] \Y[32:1] ;
...

In 6_final.v, the port name is wrongly escaped as Y\[32:1\], which caused the verilog syntax error.

72825  \ALU_33_0_33_0_33_unused_CO_X_Y[0]_KOGGE_STONE  \alu_adder_result_ex\\ALU_33_0_33_0_33_unused_CO_X_Y[0]_HAN_CARLSON  (.A({_06387_,
...
72893     .Y\[32:1\]({net1853,

Issue 2 - \alu_adder_result_ex\\ALU...

This also looks risky.

1_2_yosys.v

115119   \ALU_33_0_33_0_33_unused_CO_X_Y[0]_HAN_CARLSON  \alu_adder_result_ex\ALU_33_0_33_0_33_unused_CO_X_Y[0]_HAN_CARLSON  (

6_final.v

72825  \ALU_33_0_33_0_33_unused_CO_X_Y[0]_KOGGE_STONE  \alu_adder_result_ex\\ALU_33_0_33_0_33_unused_CO_X_Y[0]_HAN_CARLSON  (.A({_06387_,

Issue 3 - Duplicate wire names

    1 module ibex_core (alert_major_o,
...
   70  wire net;
...
20117  wire net;
...