diff --git a/.gitmodules b/.gitmodules
index bcda953424..3d4e5d0f11 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,6 +1,6 @@
 [submodule "tools/yosys"]
 	path = tools/yosys
-	url = ../../The-OpenROAD-Project/yosys.git
+	url = https://github.com/YosysHQ/yosys.git
 [submodule "tools/OpenROAD"]
 	path = tools/OpenROAD
 	url = ../OpenROAD.git
diff --git a/flow/platforms/asap7/yoSys/cells_adders_L.v b/flow/platforms/asap7/yoSys/cells_adders_L.v
index 7823593cbd..d12bd68b9b 100644
--- a/flow/platforms/asap7/yoSys/cells_adders_L.v
+++ b/flow/platforms/asap7/yoSys/cells_adders_L.v
@@ -1,6 +1,6 @@
 
-(* techmap_celltype = "$fa" *)
-module _tech_fa (A, B, C, X, Y);
+(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
+module _80_tech_fa (A, B, C, X, Y);
   parameter WIDTH = 1;
   (* force_downto *)
     input [WIDTH-1 : 0] A, B, C;
diff --git a/flow/platforms/asap7/yoSys/cells_adders_R.v b/flow/platforms/asap7/yoSys/cells_adders_R.v
index 8efcdc8d81..d76913bf51 100644
--- a/flow/platforms/asap7/yoSys/cells_adders_R.v
+++ b/flow/platforms/asap7/yoSys/cells_adders_R.v
@@ -1,6 +1,6 @@
 
-(* techmap_celltype = "$fa" *)
-module _tech_fa (A, B, C, X, Y);
+(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
+module _80_tech_fa (A, B, C, X, Y);
   parameter WIDTH = 1;
   (* force_downto *)
     input [WIDTH-1 : 0] A, B, C;
diff --git a/flow/platforms/asap7/yoSys/cells_adders_SL.v b/flow/platforms/asap7/yoSys/cells_adders_SL.v
index ab4e529339..1c28bb0f06 100644
--- a/flow/platforms/asap7/yoSys/cells_adders_SL.v
+++ b/flow/platforms/asap7/yoSys/cells_adders_SL.v
@@ -1,6 +1,6 @@
 
-(* techmap_celltype = "$fa" *)
-module _tech_fa (A, B, C, X, Y);
+(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
+module _80_tech_fa (A, B, C, X, Y);
   parameter WIDTH = 1;
   (* force_downto *)
     input [WIDTH-1 : 0] A, B, C;
diff --git a/flow/platforms/gf180/cells_adders.v b/flow/platforms/gf180/cells_adders.v
index d9a118bf01..1fd576dc4f 100644
--- a/flow/platforms/gf180/cells_adders.v
+++ b/flow/platforms/gf180/cells_adders.v
@@ -1,6 +1,6 @@
 
-(* techmap_celltype = "$fa" *)
-module _tech_fa (A, B, C, X, Y);
+(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
+module _80_tech_fa (A, B, C, X, Y);
   parameter WIDTH = 1;
   (* force_downto *)
     input [WIDTH-1 : 0] A, B, C;
diff --git a/flow/platforms/nangate45/cells_adders.v b/flow/platforms/nangate45/cells_adders.v
index f8f4dca93d..991590faf1 100644
--- a/flow/platforms/nangate45/cells_adders.v
+++ b/flow/platforms/nangate45/cells_adders.v
@@ -1,6 +1,6 @@
 
-(* techmap_celltype = "$fa" *)
-module _tech_fa (A, B, C, X, Y);
+(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
+module _80_tech_fa (A, B, C, X, Y);
   parameter WIDTH = 1;
   (* force_downto *)
     input [WIDTH-1 : 0] A, B, C;
diff --git a/flow/platforms/sky130hd/cells_adders_hd.v b/flow/platforms/sky130hd/cells_adders_hd.v
index 736d0f0dde..a57033ecd4 100644
--- a/flow/platforms/sky130hd/cells_adders_hd.v
+++ b/flow/platforms/sky130hd/cells_adders_hd.v
@@ -1,6 +1,6 @@
 
-(* techmap_celltype = "$fa" *)
-module _tech_fa (A, B, C, X, Y);
+(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
+module _80_tech_fa (A, B, C, X, Y);
   parameter WIDTH = 1;
   (* force_downto *)
     input [WIDTH-1 : 0] A, B, C;
diff --git a/flow/platforms/sky130hs/cells_adders_hs.v b/flow/platforms/sky130hs/cells_adders_hs.v
index 58d007c431..e304a01446 100644
--- a/flow/platforms/sky130hs/cells_adders_hs.v
+++ b/flow/platforms/sky130hs/cells_adders_hs.v
@@ -1,6 +1,6 @@
 
-(* techmap_celltype = "$fa" *)
-module _tech_fa (A, B, C, X, Y);
+(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
+module _80_tech_fa (A, B, C, X, Y);
   parameter WIDTH = 1;
   (* force_downto *)
     input [WIDTH-1 : 0] A, B, C;
diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl
index e800802bed..82a1852ef6 100644
--- a/flow/scripts/synth.tcl
+++ b/flow/scripts/synth.tcl
@@ -22,7 +22,13 @@ set synth_full_args $::env(SYNTH_ARGS)
 if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} {
   set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)]
 } else {
+  # Coarse LCU -> Kogge-Stone
   set synth_full_args [concat $synth_full_args "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]
+
+  if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} {
+    # Coarse FA -> PDK FA
+    set synth_full_args [concat $synth_full_args "-extra-map $::env(ADDER_MAP_FILE)"]
+  }
 }
 
 if {![env_var_equals SYNTH_HIERARCHICAL 1]} {
@@ -70,17 +76,6 @@ renames -wire
 # Optimize the design
 opt -purge
 
-# Technology mapping of adders
-if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} {
-  # extract the full adders
-  extract_fa
-  # map full adders
-  techmap -map $::env(ADDER_MAP_FILE)
-  techmap
-  # Quick optimization
-  opt -fast -purge
-}
-
 # Technology mapping of latches
 if {[env_var_exists_and_non_empty LATCH_MAP_FILE]} {
   techmap -map $::env(LATCH_MAP_FILE)
diff --git a/tools/yosys b/tools/yosys
index c4b5190229..7d560698ac 160000
--- a/tools/yosys
+++ b/tools/yosys
@@ -1 +1 @@
-Subproject commit c4b5190229616f7ebf8197f43990b4429de3e420
+Subproject commit 7d560698ac1fde66d711431b125a54a11e9e5b1d