From 3f02e5753227fba8a64fd6b357cb7f237e17a1ae Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 7 Apr 2025 17:11:49 +0200 Subject: [PATCH 1/6] synth: remove extract_fa Signed-off-by: Emil J. Tywoniak --- flow/scripts/synth.tcl | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index e800802bed..086592b747 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -72,11 +72,10 @@ opt -purge # Technology mapping of adders if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} { - # extract the full adders - extract_fa - # map full adders + # default map all but full adders + techmap -dont_map \$fa + # custom map full adders techmap -map $::env(ADDER_MAP_FILE) - techmap # Quick optimization opt -fast -purge } From 80f5e35786b91bf1db6c1da891afa4f274b27b7d Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 7 Apr 2025 19:36:47 +0200 Subject: [PATCH 2/6] cells_adders: set techmap priority to 80 Signed-off-by: Emil J. Tywoniak --- flow/platforms/asap7/yoSys/cells_adders_L.v | 2 +- flow/platforms/asap7/yoSys/cells_adders_R.v | 2 +- flow/platforms/asap7/yoSys/cells_adders_SL.v | 2 +- flow/platforms/gf180/cells_adders.v | 2 +- flow/platforms/nangate45/cells_adders.v | 2 +- flow/platforms/sky130hd/cells_adders_hd.v | 2 +- flow/platforms/sky130hs/cells_adders_hs.v | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/flow/platforms/asap7/yoSys/cells_adders_L.v b/flow/platforms/asap7/yoSys/cells_adders_L.v index 7823593cbd..f953f1a3b7 100644 --- a/flow/platforms/asap7/yoSys/cells_adders_L.v +++ b/flow/platforms/asap7/yoSys/cells_adders_L.v @@ -1,6 +1,6 @@ (* techmap_celltype = "$fa" *) -module _tech_fa (A, B, C, X, Y); +module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) input [WIDTH-1 : 0] A, B, C; diff --git a/flow/platforms/asap7/yoSys/cells_adders_R.v b/flow/platforms/asap7/yoSys/cells_adders_R.v index 8efcdc8d81..6019d93034 100644 --- a/flow/platforms/asap7/yoSys/cells_adders_R.v +++ b/flow/platforms/asap7/yoSys/cells_adders_R.v @@ -1,6 +1,6 @@ (* techmap_celltype = "$fa" *) -module _tech_fa (A, B, C, X, Y); +module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) input [WIDTH-1 : 0] A, B, C; diff --git a/flow/platforms/asap7/yoSys/cells_adders_SL.v b/flow/platforms/asap7/yoSys/cells_adders_SL.v index ab4e529339..396d637490 100644 --- a/flow/platforms/asap7/yoSys/cells_adders_SL.v +++ b/flow/platforms/asap7/yoSys/cells_adders_SL.v @@ -1,6 +1,6 @@ (* techmap_celltype = "$fa" *) -module _tech_fa (A, B, C, X, Y); +module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) input [WIDTH-1 : 0] A, B, C; diff --git a/flow/platforms/gf180/cells_adders.v b/flow/platforms/gf180/cells_adders.v index d9a118bf01..bfaa3d42b9 100644 --- a/flow/platforms/gf180/cells_adders.v +++ b/flow/platforms/gf180/cells_adders.v @@ -1,6 +1,6 @@ (* techmap_celltype = "$fa" *) -module _tech_fa (A, B, C, X, Y); +module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) input [WIDTH-1 : 0] A, B, C; diff --git a/flow/platforms/nangate45/cells_adders.v b/flow/platforms/nangate45/cells_adders.v index f8f4dca93d..a54f681cf7 100644 --- a/flow/platforms/nangate45/cells_adders.v +++ b/flow/platforms/nangate45/cells_adders.v @@ -1,6 +1,6 @@ (* techmap_celltype = "$fa" *) -module _tech_fa (A, B, C, X, Y); +module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) input [WIDTH-1 : 0] A, B, C; diff --git a/flow/platforms/sky130hd/cells_adders_hd.v b/flow/platforms/sky130hd/cells_adders_hd.v index 736d0f0dde..138d6396b8 100644 --- a/flow/platforms/sky130hd/cells_adders_hd.v +++ b/flow/platforms/sky130hd/cells_adders_hd.v @@ -1,6 +1,6 @@ (* techmap_celltype = "$fa" *) -module _tech_fa (A, B, C, X, Y); +module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) input [WIDTH-1 : 0] A, B, C; diff --git a/flow/platforms/sky130hs/cells_adders_hs.v b/flow/platforms/sky130hs/cells_adders_hs.v index 58d007c431..06e82dfdcd 100644 --- a/flow/platforms/sky130hs/cells_adders_hs.v +++ b/flow/platforms/sky130hs/cells_adders_hs.v @@ -1,6 +1,6 @@ (* techmap_celltype = "$fa" *) -module _tech_fa (A, B, C, X, Y); +module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) input [WIDTH-1 : 0] A, B, C; From eb1d9e967694da8a2615505ccfff154a128bec35 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 7 Apr 2025 19:37:54 +0200 Subject: [PATCH 3/6] synth: map adders with synth -extra-map Signed-off-by: Emil J. Tywoniak --- flow/scripts/synth.tcl | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 086592b747..82a1852ef6 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -22,7 +22,13 @@ set synth_full_args $::env(SYNTH_ARGS) if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} { set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)] } else { + # Coarse LCU -> Kogge-Stone set synth_full_args [concat $synth_full_args "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"] + + if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} { + # Coarse FA -> PDK FA + set synth_full_args [concat $synth_full_args "-extra-map $::env(ADDER_MAP_FILE)"] + } } if {![env_var_equals SYNTH_HIERARCHICAL 1]} { @@ -70,16 +76,6 @@ renames -wire # Optimize the design opt -purge -# Technology mapping of adders -if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} { - # default map all but full adders - techmap -dont_map \$fa - # custom map full adders - techmap -map $::env(ADDER_MAP_FILE) - # Quick optimization - opt -fast -purge -} - # Technology mapping of latches if {[env_var_exists_and_non_empty LATCH_MAP_FILE]} { techmap -map $::env(LATCH_MAP_FILE) From 119ff8304e6bfdc42197d6ae0a48631efe531a14 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 16 Apr 2025 22:39:40 +0200 Subject: [PATCH 4/6] Bump yosys to PR #4997 Signed-off-by: Emil J. Tywoniak --- tools/yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/yosys b/tools/yosys index c4b5190229..7d560698ac 160000 --- a/tools/yosys +++ b/tools/yosys @@ -1 +1 @@ -Subproject commit c4b5190229616f7ebf8197f43990b4429de3e420 +Subproject commit 7d560698ac1fde66d711431b125a54a11e9e5b1d From 22090f9b057899d9bd7c488f6ce9827ef6623c8b Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 17 Apr 2025 00:08:14 +0200 Subject: [PATCH 5/6] fixup! Bump yosys to PR #4997 Signed-off-by: Emil J. Tywoniak --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index bcda953424..3d4e5d0f11 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,6 @@ [submodule "tools/yosys"] path = tools/yosys - url = ../../The-OpenROAD-Project/yosys.git + url = https://github.com/YosysHQ/yosys.git [submodule "tools/OpenROAD"] path = tools/OpenROAD url = ../OpenROAD.git From 8e726879c96413c7f35bedc9b2668ac96348545b Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 30 Apr 2025 15:57:21 +0200 Subject: [PATCH 6/6] cells_adders: whitebox --- flow/platforms/asap7/yoSys/cells_adders_L.v | 2 +- flow/platforms/asap7/yoSys/cells_adders_R.v | 2 +- flow/platforms/asap7/yoSys/cells_adders_SL.v | 2 +- flow/platforms/gf180/cells_adders.v | 2 +- flow/platforms/nangate45/cells_adders.v | 2 +- flow/platforms/sky130hd/cells_adders_hd.v | 2 +- flow/platforms/sky130hs/cells_adders_hs.v | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/flow/platforms/asap7/yoSys/cells_adders_L.v b/flow/platforms/asap7/yoSys/cells_adders_L.v index f953f1a3b7..d12bd68b9b 100644 --- a/flow/platforms/asap7/yoSys/cells_adders_L.v +++ b/flow/platforms/asap7/yoSys/cells_adders_L.v @@ -1,5 +1,5 @@ -(* techmap_celltype = "$fa" *) +(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *) module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) diff --git a/flow/platforms/asap7/yoSys/cells_adders_R.v b/flow/platforms/asap7/yoSys/cells_adders_R.v index 6019d93034..d76913bf51 100644 --- a/flow/platforms/asap7/yoSys/cells_adders_R.v +++ b/flow/platforms/asap7/yoSys/cells_adders_R.v @@ -1,5 +1,5 @@ -(* techmap_celltype = "$fa" *) +(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *) module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) diff --git a/flow/platforms/asap7/yoSys/cells_adders_SL.v b/flow/platforms/asap7/yoSys/cells_adders_SL.v index 396d637490..1c28bb0f06 100644 --- a/flow/platforms/asap7/yoSys/cells_adders_SL.v +++ b/flow/platforms/asap7/yoSys/cells_adders_SL.v @@ -1,5 +1,5 @@ -(* techmap_celltype = "$fa" *) +(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *) module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) diff --git a/flow/platforms/gf180/cells_adders.v b/flow/platforms/gf180/cells_adders.v index bfaa3d42b9..1fd576dc4f 100644 --- a/flow/platforms/gf180/cells_adders.v +++ b/flow/platforms/gf180/cells_adders.v @@ -1,5 +1,5 @@ -(* techmap_celltype = "$fa" *) +(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *) module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) diff --git a/flow/platforms/nangate45/cells_adders.v b/flow/platforms/nangate45/cells_adders.v index a54f681cf7..991590faf1 100644 --- a/flow/platforms/nangate45/cells_adders.v +++ b/flow/platforms/nangate45/cells_adders.v @@ -1,5 +1,5 @@ -(* techmap_celltype = "$fa" *) +(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *) module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) diff --git a/flow/platforms/sky130hd/cells_adders_hd.v b/flow/platforms/sky130hd/cells_adders_hd.v index 138d6396b8..a57033ecd4 100644 --- a/flow/platforms/sky130hd/cells_adders_hd.v +++ b/flow/platforms/sky130hd/cells_adders_hd.v @@ -1,5 +1,5 @@ -(* techmap_celltype = "$fa" *) +(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *) module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *) diff --git a/flow/platforms/sky130hs/cells_adders_hs.v b/flow/platforms/sky130hs/cells_adders_hs.v index 06e82dfdcd..e304a01446 100644 --- a/flow/platforms/sky130hs/cells_adders_hs.v +++ b/flow/platforms/sky130hs/cells_adders_hs.v @@ -1,5 +1,5 @@ -(* techmap_celltype = "$fa" *) +(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *) module _80_tech_fa (A, B, C, X, Y); parameter WIDTH = 1; (* force_downto *)