diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md
index 3f1b488e51..c5e978cf07 100644
--- a/docs/user/FlowVariables.md
+++ b/docs/user/FlowVariables.md
@@ -95,6 +95,7 @@ configuration file.
| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | |
| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | |
| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | |
+| FLOORPLAN_BUFFERING| Perform a pre-placement buffering round at the floorplan stage.| 1| |
| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | |
| FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base| |
| GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| | |
@@ -138,7 +139,6 @@ configuration file.
| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | |
| RCX_RULES| RC Extraction rules file path.| | |
| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| |
-| REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| | yes|
| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | |
| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | |
| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| |
@@ -239,6 +239,7 @@ configuration file.
- [CORE_MARGIN](#CORE_MARGIN)
- [CORE_UTILIZATION](#CORE_UTILIZATION)
- [DIE_AREA](#DIE_AREA)
+- [FLOORPLAN_BUFFERING](#FLOORPLAN_BUFFERING)
- [FLOORPLAN_DEF](#FLOORPLAN_DEF)
- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN)
- [IO_CONSTRAINTS](#IO_CONSTRAINTS)
@@ -255,7 +256,6 @@ configuration file.
- [PLACE_DENSITY](#PLACE_DENSITY)
- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON)
- [PLACE_SITE](#PLACE_SITE)
-- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS)
- [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER)
- [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER)
- [RTLMP_AREA_WT](#RTLMP_AREA_WT)
diff --git a/flow/designs/asap7/minimal/config.mk b/flow/designs/asap7/minimal/config.mk
index ce53e6c2aa..da5f49ff09 100644
--- a/flow/designs/asap7/minimal/config.mk
+++ b/flow/designs/asap7/minimal/config.mk
@@ -19,5 +19,5 @@ export SKIP_REPORT_METRICS = 1
# Faster build, remove these in your own config.mk
export SKIP_CTS_REPAIR_TIMING = 1
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
export SKIP_INCREMENTAL_REPAIR = 1
diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk
index cfb21ab138..721702fb8d 100644
--- a/flow/designs/gf12/ariane/config.mk
+++ b/flow/designs/gf12/ariane/config.mk
@@ -36,4 +36,4 @@ else
export DESIGN_TYPE = CELL_NODEN
endif
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
diff --git a/flow/designs/gf12/ariane133/config.mk b/flow/designs/gf12/ariane133/config.mk
index 28c9649cd7..e2e4952df3 100644
--- a/flow/designs/gf12/ariane133/config.mk
+++ b/flow/designs/gf12/ariane133/config.mk
@@ -30,4 +30,4 @@ else
export DESIGN_TYPE = CELL_NODEN
endif
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk
index 2ed5601613..e7939c8f44 100644
--- a/flow/designs/gf12/swerv_wrapper/config.mk
+++ b/flow/designs/gf12/swerv_wrapper/config.mk
@@ -36,4 +36,4 @@ else
export DESIGN_TYPE = CELL_NODEN
endif
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
diff --git a/flow/designs/ihp-sg13g2/aes/config.mk b/flow/designs/ihp-sg13g2/aes/config.mk
index 5acb53d84d..85a34dfe27 100644
--- a/flow/designs/ihp-sg13g2/aes/config.mk
+++ b/flow/designs/ihp-sg13g2/aes/config.mk
@@ -13,4 +13,4 @@ export TNS_END_PERCENT = 100
export USE_FILL = 1
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
diff --git a/flow/designs/ihp-sg13g2/jpeg/config.mk b/flow/designs/ihp-sg13g2/jpeg/config.mk
index a1cfef88a4..3ff7546828 100644
--- a/flow/designs/ihp-sg13g2/jpeg/config.mk
+++ b/flow/designs/ihp-sg13g2/jpeg/config.mk
@@ -10,5 +10,5 @@ export CORE_UTILIZATION = 55
export PLACE_DENSITY_LB_ADDON = 0.20
export TNS_END_PERCENT = 100
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
diff --git a/flow/designs/sky130hd/aes/config.mk b/flow/designs/sky130hd/aes/config.mk
index 85b0da73d6..5507a1b92e 100644
--- a/flow/designs/sky130hd/aes/config.mk
+++ b/flow/designs/sky130hd/aes/config.mk
@@ -16,7 +16,7 @@ export TNS_END_PERCENT = 100
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
export CTS_CLUSTER_SIZE = 20
export CTS_CLUSTER_DIAMETER = 50
diff --git a/flow/designs/sky130hd/ibex/BUILD.bazel b/flow/designs/sky130hd/ibex/BUILD.bazel
index 7203d88313..7eada135ea 100644
--- a/flow/designs/sky130hd/ibex/BUILD.bazel
+++ b/flow/designs/sky130hd/ibex/BUILD.bazel
@@ -7,7 +7,7 @@ orfs_flow(
"CORE_UTILIZATION": "45",
"PLACE_DENSITY_LB_ADDON": "0.2",
"TNS_END_PERCENT": "100",
- "REMOVE_ABC_BUFFERS": "1",
+ "FLOORPLAN_BUFFERING": "0",
"SYNTH_HDL_FRONTEND": "slang",
"VERILOG_INCLUDE_DIRS": "flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl",
},
diff --git a/flow/designs/sky130hd/ibex/config.mk b/flow/designs/sky130hd/ibex/config.mk
index c0c930cc3e..cc7fcd1267 100644
--- a/flow/designs/sky130hd/ibex/config.mk
+++ b/flow/designs/sky130hd/ibex/config.mk
@@ -21,7 +21,7 @@ export TNS_END_PERCENT = 100
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
export CTS_CLUSTER_SIZE = 20
export CTS_CLUSTER_DIAMETER = 50
diff --git a/flow/designs/sky130hd/jpeg/config.mk b/flow/designs/sky130hd/jpeg/config.mk
index dced6f2bca..59d73fc54c 100644
--- a/flow/designs/sky130hd/jpeg/config.mk
+++ b/flow/designs/sky130hd/jpeg/config.mk
@@ -12,4 +12,4 @@ export TNS_END_PERCENT = 100
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
diff --git a/flow/designs/sky130hd/riscv32i/config.mk b/flow/designs/sky130hd/riscv32i/config.mk
index 523df1d1c1..03393e93f2 100644
--- a/flow/designs/sky130hd/riscv32i/config.mk
+++ b/flow/designs/sky130hd/riscv32i/config.mk
@@ -8,4 +8,4 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
export CORE_UTILIZATION = 45
export PLACE_DENSITY_LB_ADDON = 0.2
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
diff --git a/flow/designs/sky130hs/aes/config.mk b/flow/designs/sky130hs/aes/config.mk
index 4bf78ac5ec..dbf2941be7 100644
--- a/flow/designs/sky130hs/aes/config.mk
+++ b/flow/designs/sky130hs/aes/config.mk
@@ -12,7 +12,7 @@ export CORE_MARGIN = 2
export PLACE_DENSITY_LB_ADDON = 0.25
export TNS_END_PERCENT = 100
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
export CTS_CLUSTER_SIZE = 10
export CTS_CLUSTER_DIAMETER = 50
diff --git a/flow/designs/sky130hs/ibex/config.mk b/flow/designs/sky130hs/ibex/config.mk
index bb2959edd3..3aeb4df5ed 100644
--- a/flow/designs/sky130hs/ibex/config.mk
+++ b/flow/designs/sky130hs/ibex/config.mk
@@ -16,4 +16,4 @@ export CORE_UTILIZATION = 45
export PLACE_DENSITY_LB_ADDON = 0.2
export TNS_END_PERCENT = 100
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
diff --git a/flow/designs/sky130hs/riscv32i/config.mk b/flow/designs/sky130hs/riscv32i/config.mk
index 1cf6ab1cf9..40f3ed4dd6 100644
--- a/flow/designs/sky130hs/riscv32i/config.mk
+++ b/flow/designs/sky130hs/riscv32i/config.mk
@@ -13,4 +13,4 @@ export TNS_END_PERCENT = 100
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
-export REMOVE_ABC_BUFFERS = 1
+export FLOORPLAN_BUFFERING = 0
diff --git a/flow/scripts/abc_speed.script b/flow/scripts/abc_speed.script
index 92a702942b..1f8ba673e0 100644
--- a/flow/scripts/abc_speed.script
+++ b/flow/scripts/abc_speed.script
@@ -28,8 +28,3 @@
&synch2
&nf
&put
-buffer -c
-topo
-stime -c
-upsize -c
-dnsize -c
diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl
index 259e97d57f..63a637fb38 100644
--- a/flow/scripts/floorplan.tcl
+++ b/flow/scripts/floorplan.tcl
@@ -40,6 +40,26 @@ check_setup
set num_instances [llength [get_cells -hier *]]
puts "number instances in verilog is $num_instances"
+# Strip all incoming buffers
+remove_buffers
+
+set_dont_use $::env(DONT_USE_CELLS)
+
+# Do not buffer chip-level designs
+# by default, IO ports will be buffered
+# to not buffer IO ports, set environment variable
+# DONT_BUFFER_PORT = 1
+if { ![env_var_exists_and_non_empty FOOTPRINT] } {
+ if { ![env_var_equals DONT_BUFFER_PORTS 1] } {
+ puts "Perform port buffering..."
+ buffer_ports
+ }
+}
+
+if {[env_var_equals FLOORPLAN_BUFFERING 1]} {
+ repair_design_helper -pre_placement
+}
+
set additional_args ""
append_env_var additional_args ADDITIONAL_SITES -additional_sites 1
@@ -103,13 +123,6 @@ if {[env_var_exists_and_non_empty FOOTPRINT_TCL]} {
log_cmd source $::env(FOOTPRINT_TCL)
}
-if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
- # remove buffers inserted by yosys/abc
- remove_buffers
-} else {
- repair_timing_helper 0
-}
-
##### Restructure for timing #########
if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } {
repair_design_helper
diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl
index cb38355043..1982f9b9aa 100644
--- a/flow/scripts/resize.tcl
+++ b/flow/scripts/resize.tcl
@@ -10,17 +10,6 @@ set pin_count_before [sta::network_leaf_pin_count]
set_dont_use $::env(DONT_USE_CELLS)
-# Do not buffer chip-level designs
-# by default, IO ports will be buffered
-# to not buffer IO ports, set environment variable
-# DONT_BUFFER_PORT = 1
-if { ![env_var_exists_and_non_empty FOOTPRINT] } {
- if { ![env_var_equals DONT_BUFFER_PORTS 1] } {
- puts "Perform port buffering..."
- buffer_ports
- }
-}
-
repair_design_helper
if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl
index 0123aaab6d..5f0d0943ac 100644
--- a/flow/scripts/util.tcl
+++ b/flow/scripts/util.tcl
@@ -40,14 +40,14 @@ proc repair_timing_helper { {hold_margin 1} } {
log_cmd repair_timing {*}$additional_args
}
-proc repair_design_helper {} {
+proc repair_design_helper { {extra_args ""} } {
puts "Perform buffer insertion and gate resizing..."
- set additional_args "-verbose"
- append_env_var additional_args CAP_MARGIN -cap_margin 1
- append_env_var additional_args SLEW_MARGIN -slew_margin 1
- append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
- log_cmd repair_design {*}$additional_args
+ set args "-verbose"
+ append_env_var args CAP_MARGIN -cap_margin 1
+ append_env_var args SLEW_MARGIN -slew_margin 1
+ append_env_var args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
+ log_cmd repair_design {*}$args {*}$extra_args
}
proc recover_power_helper {} {
diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml
index 86d15317fb..63b7031032 100644
--- a/flow/scripts/variables.yaml
+++ b/flow/scripts/variables.yaml
@@ -261,14 +261,12 @@ FLOORPLAN_DEF:
stages:
- floorplan
- place
-REMOVE_ABC_BUFFERS:
+FLOORPLAN_BUFFERING:
description: >
- Remove abc buffers from the netlist. If timing repair in floorplanning is
- taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early
- instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.
+ Perform a pre-placement buffering round at the floorplan stage.
stages:
- floorplan
- deprecated: 1
+ default: 1
PLACE_SITE:
description: |
Placement site for core cells defined in the technology LEF file.