diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk
index 5144d99aec..85b00dc9be 100644
--- a/flow/designs/asap7/cva6/config.mk
+++ b/flow/designs/asap7/cva6/config.mk
@@ -95,7 +95,7 @@ export PLACE_DENSITY          = 0.69
 
 # a smoketest for this option, there are a
 # few last gasp iterations
-export SKIP_LAST_GASP ?= 1
+#export SKIP_LAST_GASP ?= 1
 
 # For use with SYNTH_HIERARCHICAL
 export SYNTH_MINIMUM_KEEP_SIZE ?= 40000
diff --git a/flow/designs/asap7/cva6/constraint.sdc b/flow/designs/asap7/cva6/constraint.sdc
index 08bf5ba873..bb2840e946 100644
--- a/flow/designs/asap7/cva6/constraint.sdc
+++ b/flow/designs/asap7/cva6/constraint.sdc
@@ -34,3 +34,4 @@ create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
 
 
 set_false_path -to [get_ports {rvfi_probes_o}]
+set_max_fanout 10 [current_design]
diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl
index 252cb77d6e..dd5a8e1cc1 100644
--- a/flow/scripts/synth.tcl
+++ b/flow/scripts/synth.tcl
@@ -84,9 +84,7 @@ chformal -remove
 delete t:\$print
 
 # rename registers to have the verilog register name in its name
-# of the form \regName$_DFF_P_. We should fix yosys to make it the reg name.
-# At least this is predictable.
-renames -wire
+renames -wire -move-to-cell
 
 # Optimize the design
 opt -purge
diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl
index fe4d69973a..8a51e55b59 100644
--- a/flow/scripts/util.tcl
+++ b/flow/scripts/util.tcl
@@ -26,6 +26,7 @@ proc repair_timing_helper { args } {
   append_env_var additional_args SKIP_BUFFER_REMOVAL -skip_buffer_removal 0
   append_env_var additional_args SKIP_LAST_GASP -skip_last_gasp 0
   append_env_var additional_args SKIP_VT_SWAP -skip_vt_swap 0
+  append_env_var additional_args SKIP_CRIT_VT_SWAP -skip_crit_vt_swap 0
   append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
   log_cmd repair_timing {*}$additional_args
 }
diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml
index 90b20123f4..f85c6216de 100644
--- a/flow/scripts/variables.yaml
+++ b/flow/scripts/variables.yaml
@@ -577,6 +577,15 @@ SKIP_VT_SWAP:
     - cts
     - floorplan
     - grt
+SKIP_CRIT_VT_SWAP:
+  description: >
+    Do not perform VT swap on critical cells to improve QoR (default: do critical VT swap).
+    This is an additional VT swap on critical cells that remain near the end of setup fixing.
+    If SKIP_VT_SWAP is set to 1, this also disables critical cell VT swap.
+  stages:
+    - cts
+    - floorplan
+    - grt
 REMOVE_CELLS_FOR_EQY:
   description: >
     String patterns directly passed to write_verilog -remove_cells <> for
diff --git a/tools/OpenROAD b/tools/OpenROAD
index 96512a37e9..a5073ecab3 160000
--- a/tools/OpenROAD
+++ b/tools/OpenROAD
@@ -1 +1 @@
-Subproject commit 96512a37e909391e63c0e2431b3850779216a465
+Subproject commit a5073ecab3cefeb441228b352255458b2ead2db1