dbNetwork: Fixed a bug where get_ports fails for top-level bus port in hierarchical flow.

Signed-off-by: Jaehyun Kim <[email protected]>

Author: jhkim-pii

src/dbSta/src/dbNetwork.cc

@@ -2012,6 +2012,8 @@ void dbNetwork::makeCell(Library* library, dbMaster* master)
   }
   // Assume msb first busses because LEF has no clue about busses.
   // This generates the top level ports
+  // TODO: MSB first assumption looks risky because there can be LSB first
+  // buses.
   groupBusPorts(cell, [](const char*) { return true; });
 
   // Fill in liberty to db/LEF master correspondence for libraries not used
@@ -3237,9 +3239,12 @@ Port* DbNetworkPortMemberIterator::next()
 
 PortMemberIterator* dbNetwork::memberIterator(const Port* port) const
 {
-  if (!hierarchy_) {
+  // top-level port is concrete port. DbNetworkPortMemberIterator cannot handle
+  // it.
+  if (!hierarchy_ || isConcretePort(port)) {
     return ConcreteNetwork::memberIterator(port);
   }
+
   return new DbNetworkPortMemberIterator(port, this);
 }
 

src/dbSta/test/CMakeLists.txt

@@ -7,6 +7,8 @@ or_integration_tests(
     constant1
     find_clks1
     find_clks2
+    get_ports1
+    get_ports1_hier
     hier2
     hierclock
     hierwrite

src/dbSta/test/get_ports1.ok

@@ -0,0 +1,72 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+clk {top_in_bus[0]} {top_in_bus[1]} {top_in_bus[2]} {top_in_bus[3]} {top_in_bus[4]} {top_in_bus[5]} {top_in_bus[6]} {top_in_bus[7]} top_in_single {top_out_bus[0]} {top_out_bus[1]} {top_out_bus[2]} {top_out_bus[3]} {top_out_bus[4]} top_out_single
+count: 16
+
+{top_in_bus[0]} {top_in_bus[1]} {top_in_bus[2]} {top_in_bus[3]} {top_in_bus[4]} {top_in_bus[5]} {top_in_bus[6]} {top_in_bus[7]}
+count: 8
+
+{top_in_bus[0]} {top_in_bus[1]} {top_in_bus[2]} {top_in_bus[3]} {top_in_bus[4]} {top_in_bus[5]} {top_in_bus[6]} {top_in_bus[7]}
+count: 8
+
+top_in_single
+count: 1
+
+top_out_single
+count: 1
+
+{top_in_bus[0]} {top_in_bus[1]} {top_in_bus[2]} {top_in_bus[3]} {top_in_bus[4]} {top_in_bus[5]} {top_in_bus[6]} {top_in_bus[7]} top_in_single
+count: 9
+
+{top_out_bus[0]} {top_out_bus[1]} {top_out_bus[2]} {top_out_bus[3]} {top_out_bus[4]} top_out_single
+count: 6
+
+clk
+count: 1
+
+[WARNING STA-0349] instance 'sub_inst' not found.
+
+count: 0
+
+[WARNING STA-0363] pin 'sub_inst/in_bus*' not found.
+
+count: 0
+
+[WARNING STA-0363] pin 'sub_inst/out_bus*' not found.
+
+count: 0
+
+[WARNING STA-0363] pin 'sub_inst/in_single*' not found.
+
+count: 0
+
+[WARNING STA-0363] pin 'sub_inst/out_single*' not found.
+
+count: 0
+
+[WARNING STA-0363] pin 'sub_inst/in*' not found.
+
+count: 0
+
+[WARNING STA-0363] pin 'sub_inst/out*' not found.
+
+count: 0
+
+[WARNING STA-0363] pin 'sub_inst/*[1]' not found.
+
+count: 0
+
+{top_in_bus[3]}
+count: 1
+
+{top_in_bus[2]}
+count: 1
+
+{top_in_bus[1]}
+count: 1
+
+{top_in_bus[0]}
+count: 1
+
+{top_in_bus[2]} {top_out_bus[2]}
+count: 2
+

src/dbSta/test/get_ports1.tcl

@@ -0,0 +1,44 @@
+# get_ports on a bus
+source "helpers.tcl"
+read_lef Nangate45/Nangate45.lef
+read_liberty Nangate45/Nangate45_typ.lib
+read_verilog get_ports1.v
+link_design top
+
+proc print_info {objs} {
+    set obj_names {}
+    foreach obj $objs {
+        lappend obj_names [get_name $obj]
+    }
+    puts "[lsort $obj_names]"
+    puts "count: [llength $objs]"
+    puts ""
+}
+
+print_info [get_ports *]
+
+# top module ports
+print_info [get_ports "top_in_bus*"]
+print_info [get_ports "top_in_bus*"]
+print_info [get_ports "top_in_single*"]
+print_info [get_ports "top_out_single*"]
+print_info [get_ports top_in*]
+print_info [get_ports top_out*]
+print_info [get_ports clk]
+
+# sub_module port - WARNINGS
+print_info [get_cells "sub_inst"]
+print_info [get_pins "sub_inst/in_bus*"]
+print_info [get_pins "sub_inst/out_bus*"]
+print_info [get_pins "sub_inst/in_single*"]
+print_info [get_pins "sub_inst/out_single*"]
+print_info [get_pins sub_inst/in*]
+print_info [get_pins sub_inst/out*]
+print_info [get_pins sub_inst/*[1]]
+
+# Test getting a bit of a bus
+print_info [get_ports top_in_bus[3]]
+print_info [get_ports top_in_bus[2]]
+print_info [get_ports top_in_bus[1]]
+print_info [get_ports top_in_bus[0]]
+print_info [get_ports *[2]]

src/dbSta/test/get_ports1.v

@@ -0,0 +1,37 @@
+// get_ports1.v
+
+module sub_module (
+  input [3:0] in_bus,
+  input       in_single,
+  output [1:0] out_bus,
+  output      out_single
+);
+  // Dummy logic
+  wire in_single_buf;
+  INV_X1 buf_inst (.A(in_single), .ZN(in_single_buf));
+  assign out_bus = in_bus[3:2];
+  assign out_single = in_single_buf;
+endmodule
+
+module top (
+  input [7:0] top_in_bus,
+  input       top_in_single,
+  output [4:0] top_out_bus,
+  output      top_out_single,
+  input       clk
+);
+
+  wire [1:0] sub_out_bus;
+  wire       sub_out_single;
+
+  sub_module sub_inst (
+    .in_bus(top_in_bus[3:0]),
+    .in_single(top_in_single),
+    .out_bus(sub_out_bus),
+    .out_single(sub_out_single)
+  );
+
+  assign top_out_bus = {top_in_bus[7:5], sub_out_bus[1], sub_out_single};
+  assign top_out_single = sub_out_bus[0];
+
+endmodule

src/dbSta/test/get_ports1_hier.ok

@@ -0,0 +1,65 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[WARNING ORD-0011] Hierarchical flow (-hier) is currently in development and may cause multiple issues. Do not use in production environments.
+clk {top_in_bus[0]} {top_in_bus[1]} {top_in_bus[2]} {top_in_bus[3]} {top_in_bus[4]} {top_in_bus[5]} {top_in_bus[6]} {top_in_bus[7]} top_in_single {top_out_bus[0]} {top_out_bus[1]} {top_out_bus[2]} {top_out_bus[3]} {top_out_bus[4]} top_out_single
+count: 16
+
+{top_in_bus[0]} {top_in_bus[1]} {top_in_bus[2]} {top_in_bus[3]} {top_in_bus[4]} {top_in_bus[5]} {top_in_bus[6]} {top_in_bus[7]}
+count: 8
+
+{top_in_bus[0]} {top_in_bus[1]} {top_in_bus[2]} {top_in_bus[3]} {top_in_bus[4]} {top_in_bus[5]} {top_in_bus[6]} {top_in_bus[7]}
+count: 8
+
+top_in_single
+count: 1
+
+top_out_single
+count: 1
+
+{top_in_bus[0]} {top_in_bus[1]} {top_in_bus[2]} {top_in_bus[3]} {top_in_bus[4]} {top_in_bus[5]} {top_in_bus[6]} {top_in_bus[7]} top_in_single
+count: 9
+
+{top_out_bus[0]} {top_out_bus[1]} {top_out_bus[2]} {top_out_bus[3]} {top_out_bus[4]} top_out_single
+count: 6
+
+clk
+count: 1
+
+sub_inst
+count: 1
+
+{in_bus[0]} {in_bus[1]} {in_bus[2]} {in_bus[3]}
+count: 4
+
+{out_bus[0]} {out_bus[1]}
+count: 2
+
+in_single
+count: 1
+
+out_single
+count: 1
+
+{in_bus[0]} {in_bus[1]} {in_bus[2]} {in_bus[3]} in_single
+count: 5
+
+{out_bus[0]} {out_bus[1]} out_single
+count: 3
+
+{in_bus[1]} {out_bus[1]}
+count: 2
+
+{top_in_bus[3]}
+count: 1
+
+{top_in_bus[2]}
+count: 1
+
+{top_in_bus[1]}
+count: 1
+
+{top_in_bus[0]}
+count: 1
+
+{top_in_bus[2]} {top_out_bus[2]}
+count: 2
+

src/dbSta/test/get_ports1_hier.tcl

@@ -0,0 +1,44 @@
+# get_ports on a bus
+source "helpers.tcl"
+read_lef Nangate45/Nangate45.lef
+read_liberty Nangate45/Nangate45_typ.lib
+read_verilog get_ports1.v
+link_design top -hier
+
+proc print_info {objs} {
+    set obj_names {}
+    foreach obj $objs {
+        lappend obj_names [get_name $obj]
+    }
+    puts "[lsort $obj_names]"
+    puts "count: [llength $objs]"
+    puts ""
+}
+
+print_info [get_ports *]
+
+# top module ports
+print_info [get_ports "top_in_bus*"]
+print_info [get_ports "top_in_bus*"]
+print_info [get_ports "top_in_single*"]
+print_info [get_ports "top_out_single*"]
+print_info [get_ports top_in*]
+print_info [get_ports top_out*]
+print_info [get_ports clk]
+
+# sub_module pins
+print_info [get_cells "sub_inst"]
+print_info [get_pins "sub_inst/in_bus*"]
+print_info [get_pins "sub_inst/out_bus*"]
+print_info [get_pins "sub_inst/in_single*"]
+print_info [get_pins "sub_inst/out_single*"]
+print_info [get_pins sub_inst/in*]
+print_info [get_pins sub_inst/out*]
+print_info [get_pins sub_inst/*[1]]
+
+# Test getting a bit of a bus
+print_info [get_ports top_in_bus[3]]
+print_info [get_ports top_in_bus[2]]
+print_info [get_ports top_in_bus[1]]
+print_info [get_ports top_in_bus[0]]
+print_info [get_ports *[2]]