Skip to content

Commit 07c8f3f

Browse files
malibertymaliberty
authored
Merge pull request #8206 from The-OpenROAD-Project-staging/no-place-with-unplaced-bterms
gpl/dpl: error out if there are unplaced bterms
2 parents cdd225d + cc0696f commit 07c8f3f

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

53 files changed

+1432
-1062
lines changed

‎src/cts/test/hier_insertion_delay.ok‎

Lines changed: 18 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2,12 +2,20 @@
22
[INFO ODB-0227] LEF file: array_tile_ins_delay.lef, created 1 library cells
33
[WARNING ORD-0011] Hierarchical flow (-hier) is currently in development and may cause multiple issues. Do not use in production environments.
44
[INFO IFP-0001] Added 857 rows of 210 site FreePDK45_38x28_10R_NP_162NW_34O.
5+
[WARNING PPL-0015] Macro inst_0 is not placed.
6+
Found 0 macro blocks.
7+
Using 2 tracks default min distance between IO pins.
8+
[INFO PPL-0001] Number of available slots 8754
9+
[INFO PPL-0002] Number of I/O 1
10+
[INFO PPL-0003] Number of I/O w/sink 1
11+
[INFO PPL-0004] Number of I/O w/o sink 0
12+
[INFO PPL-0005] Slots per section 200
13+
[INFO PPL-0008] Successfully assigned pins to sections.
14+
[INFO PPL-0012] I/O nets HPWL: 20.11 um.
515
[INFO GPL-0005] Execute conjugate gradient initial placement.
616
[INFO GPL-0002] DBU: 2000
717
[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um
818
[INFO GPL-0004] CoreBBox: ( 0.000 0.000 ) ( 39.900 1199.800 ) um
9-
[WARNING GPL-0001] clk toplevel port is not placed!
10-
Replace will regard clk is placed in (0, 0)
1119
[INFO GPL-0006] Number of instances: 279
1220
[INFO GPL-0007] Movable instances: 279
1321
[INFO GPL-0008] Fixed instances: 0
@@ -22,19 +30,19 @@
2230
[INFO GPL-0019] Utilization: 2.835 %
2331
[INFO GPL-0020] Standard cells area: 1257.116 um^2
2432
[INFO GPL-0021] Large instances area: 100.000 um^2
25-
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000012 HPWL: 40000
26-
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000012 HPWL: 40000
27-
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000012 HPWL: 40000
28-
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000012 HPWL: 40000
29-
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000012 HPWL: 40000
33+
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000012 HPWL: 1220290
34+
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000012 HPWL: 1230290
35+
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000012 HPWL: 1230290
36+
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000012 HPWL: 1230290
37+
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000012 HPWL: 1230290
3038
Placement Analysis
3139
---------------------------------
3240
total displacement 9363.8 u
3341
average displacement 33.6 u
3442
max displacement 51.7 u
35-
original HPWL 10.1 u
36-
legalized HPWL 91.3 u
37-
delta HPWL 806 %
43+
original HPWL 605.2 u
44+
legalized HPWL 641.6 u
45+
delta HPWL 6 %
3846

3947
[INFO CTS-0050] Root buffer is CLKBUF_X3.
4048
[INFO CTS-0051] Sink buffer is CLKBUF_X3.

‎src/cts/test/hier_insertion_delay.tcl‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,10 @@ link_design -hier multi_sink
1111
initialize_floorplan -die_area "0 0 40 1200" -core_area "0 0 40 1200" \
1212
-site FreePDK45_38x28_10R_NP_162NW_34O
1313
#make_io_sites -horizontal_site IOSITE -vertical_site IOSITE -corner_site IOSITE -offset 15
14+
source $tracks_file
15+
16+
place_pins -hor_layers $io_placer_hor_layer \
17+
-ver_layers $io_placer_ver_layer
1418
global_placement -skip_nesterov_place
1519
detailed_placement
1620

‎src/cts/test/simple_test_hier.ok‎

Lines changed: 25 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,19 @@
11
[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
22
[WARNING ORD-0011] Hierarchical flow (-hier) is currently in development and may cause multiple issues. Do not use in production environments.
33
[INFO IFP-0001] Added 857 rows of 210 site FreePDK45_38x28_10R_NP_162NW_34O.
4+
Found 0 macro blocks.
5+
Using 2 tracks default min distance between IO pins.
6+
[INFO PPL-0001] Number of available slots 8754
7+
[INFO PPL-0002] Number of I/O 1
8+
[INFO PPL-0003] Number of I/O w/sink 1
9+
[INFO PPL-0004] Number of I/O w/o sink 0
10+
[INFO PPL-0005] Slots per section 200
11+
[INFO PPL-0008] Successfully assigned pins to sections.
12+
[INFO PPL-0012] I/O nets HPWL: 20.11 um.
413
[INFO GPL-0005] Execute conjugate gradient initial placement.
514
[INFO GPL-0002] DBU: 2000
615
[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um
716
[INFO GPL-0004] CoreBBox: ( 0.000 0.000 ) ( 39.900 1199.800 ) um
8-
[WARNING GPL-0001] clk toplevel port is not placed!
9-
Replace will regard clk is placed in (0, 0)
1017
[INFO GPL-0006] Number of instances: 16
1118
[INFO GPL-0007] Movable instances: 16
1219
[INFO GPL-0008] Fixed instances: 0
@@ -21,18 +28,18 @@
2128
[INFO GPL-0019] Utilization: 0.151 %
2229
[INFO GPL-0020] Standard cells area: 72.352 um^2
2330
[INFO GPL-0021] Large instances area: 0.000 um^2
24-
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000012 HPWL: 9260
25-
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000012 HPWL: 9260
26-
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000012 HPWL: 9260
27-
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000012 HPWL: 9260
28-
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000012 HPWL: 9260
31+
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000000 HPWL: 1206750
32+
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000010 HPWL: 9260
33+
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000010 HPWL: 9260
34+
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 9260
35+
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000010 HPWL: 9260
2936
Placement Analysis
3037
---------------------------------
31-
total displacement 128.5 u
32-
average displacement 8.0 u
33-
max displacement 11.9 u
38+
total displacement 91.9 u
39+
average displacement 5.7 u
40+
max displacement 8.3 u
3441
original HPWL 0.0 u
35-
legalized HPWL 18.1 u
42+
legalized HPWL 20.8 u
3643
delta HPWL 0 %
3744

3845
[INFO CTS-0050] Root buffer is CLKBUF_X3.
@@ -49,14 +56,14 @@ delta HPWL 0 %
4956
[INFO CTS-0028] Total number of sinks: 16.
5057
[INFO CTS-0030] Number of static layers: 0.
5158
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
52-
[INFO CTS-0023] Original sink region: [(3230, 1230), (22610, 18030)].
53-
[INFO CTS-0024] Normalized sink region: [(0.230714, 0.0878571), (1.615, 1.28786)].
54-
[INFO CTS-0025] Width: 1.3843.
55-
[INFO CTS-0026] Height: 1.2000.
59+
[INFO CTS-0023] Original sink region: [(3230, 1188430), (16150, 1213970)].
60+
[INFO CTS-0024] Normalized sink region: [(0.230714, 84.8879), (1.15357, 86.7121)].
61+
[INFO CTS-0025] Width: 0.9229.
62+
[INFO CTS-0026] Height: 1.8243.
5663
Level 1
57-
Direction: Horizontal
64+
Direction: Vertical
5865
Sinks per sub-region: 8
59-
Sub-region size: 0.6921 X 1.2000
66+
Sub-region size: 0.9229 X 0.9121
6067
[INFO CTS-0034] Segment length (rounded): 1.
6168
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
6269
[INFO CTS-0035] Number of sinks covered: 16.
@@ -70,7 +77,7 @@ delta HPWL 0 %
7077
[INFO CTS-0098] Clock net "clk"
7178
[INFO CTS-0099] Sinks 17
7279
[INFO CTS-0100] Leaf buffers 0
73-
[INFO CTS-0101] Average sink wire length 22.90 um
80+
[INFO CTS-0101] Average sink wire length 17.16 um
7481
[INFO CTS-0102] Path depth 2 - 2
7582
[INFO CTS-0207] Leaf load cells 1
7683
No differences found.

‎src/cts/test/simple_test_hier.tcl‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,10 @@ source Nangate45/Nangate45.vars
1313
source Nangate45/Nangate45.rc
1414

1515
#place_pad -master PADCELL_SIG_V -row IO_EAST -location 500 "clk"
16+
source $tracks_file
17+
18+
place_pins -hor_layers $io_placer_hor_layer \
19+
-ver_layers $io_placer_ver_layer
1620

1721
global_placement -skip_nesterov_place
1822
detailed_placement

‎src/cts/test/simple_test_hier_out.vok‎

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,10 @@ module test_16_sinks (clk);
2323
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
2424
flop_pair_U6 U6 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
2525
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
26-
flop_pair_U7 U7 (.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
27-
flop_pair_U8 U8 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk));
26+
flop_pair_U7 U7 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
27+
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
28+
flop_pair_U8 U8 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
29+
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
2830
endmodule
2931
module flop_pair (clknet_1_0__leaf_clk_i);
3032
input clknet_1_0__leaf_clk_i;
@@ -39,17 +41,17 @@ module flop_pair_U2 (clknet_1_1__leaf_clk_i,
3941
input clknet_1_0__leaf_clk_i;
4042

4143

42-
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
43-
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
44+
DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
45+
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
4446
endmodule
4547
module flop_pair_U3 (clknet_1_1__leaf_clk_i,
4648
clknet_1_0__leaf_clk_i);
4749
input clknet_1_1__leaf_clk_i;
4850
input clknet_1_0__leaf_clk_i;
4951

5052

51-
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
52-
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
53+
DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
54+
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
5355
endmodule
5456
module flop_pair_U4 (clknet_1_1__leaf_clk_i,
5557
clknet_1_0__leaf_clk_i);
@@ -75,20 +77,24 @@ module flop_pair_U6 (clknet_1_1__leaf_clk_i,
7577
input clknet_1_0__leaf_clk_i;
7678

7779

78-
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
79-
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
80+
DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
81+
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
8082
endmodule
81-
module flop_pair_U7 (clknet_1_0__leaf_clk_i);
83+
module flop_pair_U7 (clknet_1_1__leaf_clk_i,
84+
clknet_1_0__leaf_clk_i);
85+
input clknet_1_1__leaf_clk_i;
8286
input clknet_1_0__leaf_clk_i;
8387

8488

8589
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
86-
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
90+
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
8791
endmodule
88-
module flop_pair_U8 (clknet_1_1__leaf_clk_i);
92+
module flop_pair_U8 (clknet_1_1__leaf_clk_i,
93+
clknet_1_0__leaf_clk_i);
8994
input clknet_1_1__leaf_clk_i;
95+
input clknet_1_0__leaf_clk_i;
9096

9197

92-
DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
98+
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
9399
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
94100
endmodule

‎src/dpl/src/dbToOpendp.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,11 @@ void Opendp::createNetwork()
137137
if (!net || net->getSigType().isSupply()) {
138138
continue;
139139
}
140+
if (bterm->getBBox().isInverted()) {
141+
logger_->error(
142+
utl::DPL, 386, "BTerm {} has no shapes.", bterm->getName());
143+
}
144+
140145
network_->addNode(bterm);
141146
}
142147

‎src/dpl/test/edge_spacing.defok‎

Lines changed: 24 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -43,12 +43,30 @@ COMPONENTS 25 ;
4343
- u2 MOCK_DOUBLE + PLACED ( 7220 11200 ) N ;
4444
END COMPONENTS
4545
PINS 6 ;
46-
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL ;
47-
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL ;
48-
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ;
49-
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL ;
50-
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL ;
51-
- out + NET out + DIRECTION OUTPUT + USE SIGNAL ;
46+
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL
47+
+ PORT
48+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
49+
+ PLACED ( 2470 70 ) N ;
50+
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL
51+
+ PORT
52+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
53+
+ PLACED ( 3230 70 ) N ;
54+
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL
55+
+ PORT
56+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
57+
+ PLACED ( 3990 70 ) N ;
58+
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL
59+
+ PORT
60+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
61+
+ PLACED ( 4750 70 ) N ;
62+
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL
63+
+ PORT
64+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
65+
+ PLACED ( 5510 70 ) N ;
66+
- out + NET out + DIRECTION OUTPUT + USE SIGNAL
67+
+ PORT
68+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
69+
+ PLACED ( 6270 70 ) N ;
5270
END PINS
5371
NETS 6 ;
5472
- clk1 ( PIN clk1 ) + USE SIGNAL ;

‎src/dpl/test/hybrid_cells.def‎

Lines changed: 24 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1012,11 +1012,29 @@ COMPONENTS 5 ;
10121012
- g3 MOCK_HYBRID_G + PLACED ( 200260 204800 ) N ;
10131013
END COMPONENTS
10141014
PINS 6 ;
1015-
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL ;
1016-
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL ;
1017-
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ;
1018-
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL ;
1019-
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL ;
1020-
- out + NET out + DIRECTION OUTPUT + USE SIGNAL ;
1015+
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL
1016+
+ PORT
1017+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1018+
+ PLACED ( 2470 70 ) N ;
1019+
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL
1020+
+ PORT
1021+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1022+
+ PLACED ( 3230 70 ) N ;
1023+
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL
1024+
+ PORT
1025+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1026+
+ PLACED ( 3990 70 ) N ;
1027+
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL
1028+
+ PORT
1029+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1030+
+ PLACED ( 4750 70 ) N ;
1031+
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL
1032+
+ PORT
1033+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1034+
+ PLACED ( 5510 70 ) N ;
1035+
- out + NET out + DIRECTION OUTPUT + USE SIGNAL
1036+
+ PORT
1037+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1038+
+ PLACED ( 6270 70 ) N ;
10211039
END PINS
10221040
END DESIGN

‎src/dpl/test/hybrid_cells.defok‎

Lines changed: 24 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1011,12 +1011,30 @@ COMPONENTS 10 ;
10111011
- u3 MOCK_HYBRID_AG + PLACED ( 200260 204800 ) N ;
10121012
END COMPONENTS
10131013
PINS 6 ;
1014-
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL ;
1015-
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL ;
1016-
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ;
1017-
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL ;
1018-
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL ;
1019-
- out + NET out + DIRECTION OUTPUT + USE SIGNAL ;
1014+
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL
1015+
+ PORT
1016+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1017+
+ PLACED ( 2470 70 ) N ;
1018+
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL
1019+
+ PORT
1020+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1021+
+ PLACED ( 3230 70 ) N ;
1022+
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL
1023+
+ PORT
1024+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1025+
+ PLACED ( 3990 70 ) N ;
1026+
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL
1027+
+ PORT
1028+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1029+
+ PLACED ( 4750 70 ) N ;
1030+
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL
1031+
+ PORT
1032+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1033+
+ PLACED ( 5510 70 ) N ;
1034+
- out + NET out + DIRECTION OUTPUT + USE SIGNAL
1035+
+ PORT
1036+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1037+
+ PLACED ( 6270 70 ) N ;
10201038
END PINS
10211039
NETS 6 ;
10221040
- clk1 ( PIN clk1 ) + USE SIGNAL ;

‎src/dpl/test/hybrid_cells2.def‎

Lines changed: 24 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1013,11 +1013,29 @@ COMPONENTS 5 ;
10131013
- g3 MOCK_HYBRID_G + PLACED ( 200260 204800 ) N ;
10141014
END COMPONENTS
10151015
PINS 6 ;
1016-
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL ;
1017-
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL ;
1018-
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ;
1019-
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL ;
1020-
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL ;
1021-
- out + NET out + DIRECTION OUTPUT + USE SIGNAL ;
1016+
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL
1017+
+ PORT
1018+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1019+
+ PLACED ( 2470 70 ) N ;
1020+
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL
1021+
+ PORT
1022+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1023+
+ PLACED ( 3230 70 ) N ;
1024+
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL
1025+
+ PORT
1026+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1027+
+ PLACED ( 3990 70 ) N ;
1028+
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL
1029+
+ PORT
1030+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1031+
+ PLACED ( 4750 70 ) N ;
1032+
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL
1033+
+ PORT
1034+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1035+
+ PLACED ( 5510 70 ) N ;
1036+
- out + NET out + DIRECTION OUTPUT + USE SIGNAL
1037+
+ PORT
1038+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
1039+
+ PLACED ( 6270 70 ) N ;
10221040
END PINS
10231041
END DESIGN

0 commit comments

Comments
 (0)