test/orfs/ram_8x7: eqy_floorplan_test failure

Disabled for now, but this ram_8x7.sv is the smallest file that we've
found to work in simulation before floorplan and fail afterwards:

    bazelisk test //test/orfs/ram_8x7:eqy_floorplan_test --test_output=streamed

It is a lot to hope for, but perhaps this is actionable information?

```
EQY 12:13:50 [eqy_floorplan_test] partition: ERROR: conflicting matches for gold bit \W0_en: \W0_en vs \_113_
```

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

test/orfs/ram_8x7/BUILD

@@ -0,0 +1,87 @@
+load("@bazel-orfs//:eqy.bzl", "eqy_test")
+load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_run")
+load("//test/orfs/mock-array:mock-array.bzl", "ASAP7_REMOVE_CELLS")
+
+package(features = ["layering_check"])
+
+orfs_flow(
+    name = "ram_8x7",
+    # buildifier: disable=unsorted-dict-items
+    arguments = {
+        # Faster builds
+        "GPL_TIMING_DRIVEN": "0",
+        "SKIP_INCREMENTAL_REPAIR": "1",
+        "SKIP_LAST_GASP": "1",
+        # Various
+        "CORE_AREA": "1.08 1.08 15.12 15.12",
+        "DIE_AREA": "0 0 16.2 16.2",
+        "PLACE_DENSITY": "0.35",
+        "OPENROAD_HIERARCHICAL": "1",
+    },
+    sources = {
+        "RULES_JSON": [":rules-base.json"],
+        "SDC_FILE": [":constraint.sdc"],
+    },
+    tags = ["manual"],
+    test_kwargs = {
+        "tags": ["orfs"],
+    },
+    verilog_files = ["ram_8x7.sv"],
+)
+
+STAGES = [
+    "source",
+    # _source tests original source to source transition,
+    # which checks that the eqy setup works.
+    "source",
+    # _synth tests synthesis output, and so on
+    # for the next stages.
+    "synth",
+    "floorplan",
+    "place",
+    "cts",
+    "grt",
+    "route",
+    "final",
+]
+
+[orfs_run(
+    name = "ram_8x7_{stage}_verilog".format(stage = stage),
+    src = ":ram_8x7_{stage}".format(stage = stage),
+    outs = [
+        "ram_8x7_{stage}.v".format(stage = stage),
+    ],
+    arguments = {
+        "ASAP7_REMOVE_CELLS": " ".join(ASAP7_REMOVE_CELLS),
+        "OUTPUT": "$(location :ram_8x7_{stage}.v)".format(stage = stage),
+    },
+    script = "//test/orfs/mock-array:write_verilog.tcl",
+    tags = ["manual"],
+) for stage in STAGES[2:]]
+
+filegroup(
+    name = "ram_8x7_source_files",
+    srcs = [
+        "ram_8x7.sv",
+    ],
+)
+
+[filegroup(
+    name = "ram_8x7_{stage}_files".format(stage = stage),
+    srcs = [
+        ":ram_8x7_{stage}_verilog".format(stage = stage),
+    ],
+) for stage in STAGES[2:]]
+
+[eqy_test(
+    name = "eqy_{stage}_test".format(stage = STAGES[i + 1]),
+    depth = 1,
+    gate_verilog_files = [
+        ":ram_8x7_{stage}_files".format(stage = STAGES[i + 1]),
+    ] + ([] if STAGES[i + 1] == "source" else ["//test/orfs/mock-array:asap7_files"]),
+    gold_verilog_files = [
+        ":ram_8x7_{stage}_files".format(stage = STAGES[i]),
+    ] + ([] if STAGES[i] == "source" else ["//test/orfs/mock-array:asap7_files"]),
+    module_top = "ram_8x7",
+    tags = ["manual"],
+) for i in range(len(STAGES) - 1)]

test/orfs/ram_8x7/README.md

@@ -0,0 +1,3 @@
+# Summary
+
+The main value here is that this caused eqy_floorplan_test to fail.

test/orfs/ram_8x7/constraint.sdc

@@ -0,0 +1,39 @@
+set sdc_version 2.0
+
+#
+# SDC file used during SRAM abstract generation
+#
+
+# Run at 833 MHz
+set clk_period 1200
+
+# Covers all clock naming types in SRAMs and reg files
+set clock_ports [concat [get_ports -quiet *clk] [get_ports -quiet *clock]]
+
+if {[llength $clock_ports] == 0} {
+  error "No clock ports found"
+}
+
+foreach clk_port $clock_ports {
+  set clk_name [get_name $clk_port]
+  create_clock -period $clk_period -name $clk_name $clk_port
+}
+
+set non_clk_inputs {}
+foreach input [all_inputs] {
+  if {[lsearch -exact $clock_ports $input] == -1} {
+    lappend non_clk_inputs $input
+  }
+}
+
+set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs]
+group_path -name in2out -from $non_clk_inputs -to [all_outputs]
+
+if {[llength [all_registers]] > 0} {
+  set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers]
+  set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from [all_registers] -to [all_outputs]
+
+  group_path -name in2reg -from $non_clk_inputs -to [all_registers]
+  group_path -name reg2out -from [all_registers] -to [all_outputs]
+  group_path -name reg2reg -from [all_registers] -to [all_registers]
+}

test/orfs/ram_8x7/ram_8x7.sv

@@ -0,0 +1,21 @@
+// Generated by CIRCT firtool-1.137.0
+// VCS coverage exclude_file
+module ram_8x7(
+  input  [2:0] R0_addr,
+  input        R0_en,
+               R0_clk,
+  output [6:0] R0_data,
+  input  [2:0] W0_addr,
+  input        W0_en,
+               W0_clk,
+  input  [6:0] W0_data
+);
+
+  reg [6:0] Memory[0:7];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  assign R0_data = R0_en ? Memory[R0_addr] : 7'bx;
+endmodule
+