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Merge pull request #7094 from mikesinouye/mpl
mpl: fix crash when LEF PIN specifies USE CLOCK
2 parents bcfd59a + 2d75bd0 commit 08f60ff

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10 files changed

+923
-1
lines changed

10 files changed

+923
-1
lines changed

‎src/mpl/src/clusterEngine.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -682,7 +682,8 @@ void ClusteringEngine::computeMacroPinVertices(VerticesMaps& vertices_maps)
682682
{
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for (auto& [macro, hard_macro] : tree_->maps.inst_to_hard) {
684684
for (odb::dbITerm* pin : macro->getITerms()) {
685-
if (pin->getSigType() != odb::dbSigType::SIGNAL) {
685+
if (pin->getSigType() != odb::dbSigType::SIGNAL
686+
&& pin->getSigType() != odb::dbSigType::CLOCK) {
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continue;
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}
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‎src/mpl/test/BUILD‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ COMPULSORY_TESTS = [
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"boundary_push2",
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"boundary_push3",
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"centralization1",
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"clocked_macro",
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]
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# Disabled in CMakeLists.txt
@@ -82,6 +83,10 @@ filegroup(
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"testcases/no_unfixed_macros.def",
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"testcases/orientation_improve1.def",
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"testcases/orientation_improve1.lef",
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"testcases/clocked_macro.def",
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"testcases/clocked_macro.v",
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"testcases/clocked_macro.lib",
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"testcases/clocked_macro.lef",
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],
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)
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‎src/mpl/test/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ or_integration_tests(
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boundary_push2
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boundary_push3
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centralization1
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clocked_macro
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)
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# Skipped

‎src/mpl/test/clocked_macro.defok‎

Lines changed: 349 additions & 0 deletions
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‎src/mpl/test/clocked_macro.ok‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
[INFO ODB-0227] LEF file: ./Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias
2+
[INFO ODB-0227] LEF file: ./testcases/clocked_macro.lef, created 1 library cells
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[WARNING STA-1171] ./testcases/clocked_macro.lib line 32, default_max_transition is 0.0.
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[INFO ODB-0128] Design: clocked_macro
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[INFO ODB-0253] Updated 1 components.
6+
Die Area: (0.00, 0.00) (450.00, 450.00), Floorplan Area: (4.94, 4.20) (444.98, 443.80)
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Number of std cell instances: 0
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Area of std cell instances: 0.00
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Number of macros: 1
10+
Area of macros: 43000.00
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Halo width: 4.00
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Halo height: 4.00
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Area of macros with halos: 47304.00
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Area of std cell instances + Area of macros: 43000.00
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Floorplan area: 193441.58
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Design Utilization: 0.22
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Floorplan Utilization: 0.00
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Manufacturing Grid: 10
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[WARNING MPL-0026] Design has no IO pins!
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[WARNING MPL-0025] Design has no standard cells!
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[WARNING MPL-0027] Design has only macros!
23+
No differences found.

‎src/mpl/test/clocked_macro.tcl‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
# Case in which we verify macros with CLOCK pins can
2+
# be placed.
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source "helpers.tcl"
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read_lef "./Nangate45/Nangate45_tech.lef"
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read_lef "./testcases/clocked_macro.lef"
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read_liberty "./testcases/clocked_macro.lib"
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read_verilog "./testcases/clocked_macro.v"
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link_design "clocked_macro"
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read_def "./testcases/clocked_macro.def" -floorplan_initialize
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set_thread_count 0
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rtl_macro_placer -report_directory results/clocked_macro -halo_width 4.0
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set def_file [make_result_file clocked_macro.def]
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write_def $def_file
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diff_files clocked_macro.defok $def_file

‎src/mpl/test/testcases/clocked_macro.def‎

Lines changed: 344 additions & 0 deletions
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‎src/mpl/test/testcases/clocked_macro.lef‎

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,82 @@
1+
VERSION 5.6 ;
2+
BUSBITCHARS "[]" ;
3+
DIVIDERCHAR "/" ;
4+
5+
MACRO CLOCKED_MACRO
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CLASS BLOCK ;
7+
FOREIGN CLOCKED_MACRO 0 0 ;
8+
ORIGIN 0 0 ;
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SYMMETRY X Y ;
10+
SIZE 100 BY 430 ;
11+
PIN I1
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DIRECTION INPUT ;
13+
PORT
14+
LAYER metal3 ;
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RECT 0 210 0.140 210.070 ;
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END
17+
END I1
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PIN CK
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DIRECTION INPUT ;
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USE CLOCK ;
21+
PORT
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LAYER metal3 ;
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RECT 0 210.280 0.140 210.350 ;
24+
END
25+
END CK
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PIN O1
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DIRECTION OUTPUT ;
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PORT
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LAYER metal3 ;
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RECT 99.860 210 100 210.070 ;
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END
32+
END O1
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OBS
34+
LAYER metal3 ;
35+
RECT 0 0 100 430 ;
36+
END
37+
END CLOCKED_MACRO
38+
39+
SITE DoubleHeightSite
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SYMMETRY X Y ;
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CLASS core ;
42+
SIZE 0.19 BY 2.8 ;
43+
END DoubleHeightSite
44+
45+
SITE TripleHeightSite
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SYMMETRY Y ;
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CLASS core ;
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SIZE 0.19 BY 4.2 ;
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END TripleHeightSite
50+
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SITE HybridG
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SYMMETRY X Y ;
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CLASS core ;
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SIZE 0.19 BY 1.4 ;
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END HybridG
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57+
SITE HybridA
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SYMMETRY X Y ;
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CLASS core ;
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SIZE 0.19 BY 1.8 ;
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END HybridA
62+
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SITE HybridAG
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SYMMETRY X Y ;
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CLASS core ;
66+
SIZE 0.19 BY 3.2 ;
67+
ROWPATTERN HybridA N HybridG FS ;
68+
END HybridAG
69+
70+
SITE HybridAG2
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SYMMETRY X Y ;
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CLASS core ;
73+
SIZE 0.19 BY 3.2 ;
74+
ROWPATTERN HybridA FS HybridG N ;
75+
END HybridAG2
76+
77+
SITE HybridGA
78+
SYMMETRY X Y ;
79+
CLASS core ;
80+
SIZE 0.19 BY 3.2 ;
81+
ROWPATTERN HybridG FS HybridA N ;
82+
END HybridGA

‎src/mpl/test/testcases/clocked_macro.lib‎

Lines changed: 90 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,90 @@
1+
library(fake_macros) {
2+
technology (cmos);
3+
delay_model : table_lookup;
4+
revision : 1.0;
5+
date : "2019-11-05 15:53:47Z";
6+
comment : "SRAM";
7+
time_unit : "1ns";
8+
voltage_unit : "1V";
9+
current_unit : "1mA";
10+
leakage_power_unit : "1mW";
11+
nom_process : 1;
12+
nom_temperature : 25.000;
13+
nom_voltage : 1.1;
14+
capacitive_load_unit (1,pf);
15+
16+
pulling_resistance_unit : "1kohm";
17+
18+
operating_conditions(tt_1.0_25.0) {
19+
process : 1;
20+
temperature : 25.000;
21+
voltage : 1.1;
22+
tree_type : balanced_tree;
23+
}
24+
25+
/* default attributes */
26+
default_cell_leakage_power : 0;
27+
default_fanout_load : 1;
28+
default_inout_pin_cap : 0.0;
29+
default_input_pin_cap : 0.0;
30+
default_output_pin_cap : 0.0;
31+
default_input_pin_cap : 0.0;
32+
default_max_transition : 0.0;
33+
34+
default_operating_conditions : tt_1.0_25.0;
35+
default_leakage_power_density : 0.0;
36+
37+
/* additional header data */
38+
slew_derate_from_library : 1.000;
39+
slew_lower_threshold_pct_fall : 10.000;
40+
slew_upper_threshold_pct_fall : 90.000;
41+
slew_lower_threshold_pct_rise : 10.000;
42+
slew_upper_threshold_pct_rise : 90.000;
43+
input_threshold_pct_fall : 50.000;
44+
input_threshold_pct_rise : 50.000;
45+
output_threshold_pct_fall : 50.000;
46+
output_threshold_pct_rise : 50.000;
47+
48+
49+
lu_table_template(fakeram45_64x7_mem_out_delay_template) {
50+
variable_1 : input_net_transition;
51+
variable_2 : total_output_net_capacitance;
52+
index_1 ("1000, 1001");
53+
index_2 ("1000, 1001");
54+
}
55+
lu_table_template(fakeram45_64x7_mem_out_slew_template) {
56+
variable_1 : total_output_net_capacitance;
57+
index_1 ("1000, 1001");
58+
}
59+
lu_table_template(fakeram45_64x7_constraint_template) {
60+
variable_1 : related_pin_transition;
61+
variable_2 : constrained_pin_transition;
62+
index_1 ("1000, 1001");
63+
index_2 ("1000, 1001");
64+
}
65+
power_lut_template(fakeram45_64x7_energy_template_clkslew) {
66+
variable_1 : input_transition_time;
67+
index_1 ("1000, 1001");
68+
}
69+
power_lut_template(fakeram45_64x7_energy_template_sigslew) {
70+
variable_1 : input_transition_time;
71+
index_1 ("1000, 1001");
72+
}
73+
library_features(report_delay_calculation);
74+
75+
cell(CLOCKED_MACRO) {
76+
area : 40000;
77+
interface_timing : true;
78+
is_macro : true;
79+
80+
pin (I1) {
81+
direction : input;
82+
}
83+
pin (CK) {
84+
direction : input;
85+
}
86+
pin (O1) {
87+
direction : output;
88+
}
89+
}
90+
}

‎src/mpl/test/testcases/clocked_macro.v‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
module clocked_macro ( );
2+
wire in, clk, out;
3+
4+
CLOCKED_MACRO U1 ( .I1(in), .CK(clk), .O1(out) ) ;
5+
6+
endmodule
7+

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