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calewiscalewis
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Update tests
Signed-off-by: Drew Lewis <[email protected]>
1 parent 45845da commit 0ff4613

37 files changed

+47830
-47878
lines changed

‎src/cts/test/array.ok‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -125,11 +125,11 @@ Dummys used:
125125
[INFO RSZ-0048] Inserted 112 buffers in 38 nets.
126126
Placement Analysis
127127
---------------------------------
128-
total displacement 4567.0 u
128+
total displacement 4569.6 u
129129
average displacement 1.4 u
130130
max displacement 146.7 u
131131
original HPWL 189367.9 u
132-
legalized HPWL 190335.5 u
132+
legalized HPWL 190345.7 u
133133
delta HPWL 1 %
134134

135135
Clock clk
@@ -177,9 +177,9 @@ Path Type: max
177177
0.04 1.11 ^ wire10/Z (BUF_X8)
178178
0.05 1.16 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
179179
0.00 1.16 ^ inst_1_1/clk (array_tile)
180-
0.21 1.38 ^ inst_1_1/e_out (array_tile)
181-
0.00 1.38 ^ inst_2_1/w_in (array_tile)
182-
1.38 data arrival time
180+
0.21 1.37 ^ inst_1_1/e_out (array_tile)
181+
0.00 1.37 ^ inst_2_1/w_in (array_tile)
182+
1.37 data arrival time
183183

184184
5.00 5.00 clock clk (rise edge)
185185
0.00 5.00 clock source latency
@@ -216,7 +216,7 @@ Path Type: max
216216
6.07 data required time
217217
---------------------------------------------------------
218218
6.07 data required time
219-
-1.38 data arrival time
219+
-1.37 data arrival time
220220
---------------------------------------------------------
221221
4.69 slack (MET)
222222

‎src/cts/test/array_ins_delay.ok‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -115,11 +115,11 @@
115115
[INFO RSZ-0048] Inserted 112 buffers in 38 nets.
116116
Placement Analysis
117117
---------------------------------
118-
total displacement 4576.2 u
118+
total displacement 4577.7 u
119119
average displacement 1.4 u
120120
max displacement 146.7 u
121121
original HPWL 189368.6 u
122-
legalized HPWL 190344.8 u
122+
legalized HPWL 190349.6 u
123123
delta HPWL 1 %
124124

125125
Clock clk
@@ -167,9 +167,9 @@ Path Type: max
167167
0.04 1.11 ^ wire10/Z (BUF_X8)
168168
0.05 1.16 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
169169
0.00 1.16 ^ inst_1_1/clk (array_tile)
170-
0.21 1.38 ^ inst_1_1/e_out (array_tile)
171-
0.00 1.38 ^ inst_2_1/w_in (array_tile)
172-
1.38 data arrival time
170+
0.21 1.37 ^ inst_1_1/e_out (array_tile)
171+
0.00 1.37 ^ inst_2_1/w_in (array_tile)
172+
1.37 data arrival time
173173

174174
5.00 5.00 clock clk (rise edge)
175175
0.00 5.00 clock source latency
@@ -206,7 +206,7 @@ Path Type: max
206206
6.07 data required time
207207
---------------------------------------------------------
208208
6.07 data required time
209-
-1.38 data arrival time
209+
-1.37 data arrival time
210210
---------------------------------------------------------
211211
4.69 slack (MET)
212212

‎src/cts/test/array_no_blockages.ok‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -114,11 +114,11 @@
114114
[INFO RSZ-0048] Inserted 112 buffers in 38 nets.
115115
Placement Analysis
116116
---------------------------------
117-
total displacement 4366.2 u
117+
total displacement 4368.8 u
118118
average displacement 1.4 u
119119
max displacement 146.3 u
120120
original HPWL 190067.1 u
121-
legalized HPWL 191162.0 u
121+
legalized HPWL 191160.9 u
122122
delta HPWL 1 %
123123

124124
Clock clk

‎src/cts/test/array_repair_clock_nets.ok‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -128,11 +128,11 @@ Dummys used:
128128
[INFO RSZ-0058] Using max wire length 693um.
129129
Placement Analysis
130130
---------------------------------
131-
total displacement 4508.1 u
131+
total displacement 4509.5 u
132132
average displacement 1.4 u
133133
max displacement 146.7 u
134134
original HPWL 189361.4 u
135-
legalized HPWL 190291.0 u
135+
legalized HPWL 190300.6 u
136136
delta HPWL 0 %
137137

138138
Clock clk

‎src/cts/test/simple_test_hier.ok‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ delta HPWL 0 %
7777
[INFO CTS-0098] Clock net "clk"
7878
[INFO CTS-0099] Sinks 17
7979
[INFO CTS-0100] Leaf buffers 0
80-
[INFO CTS-0101] Average sink wire length 17.16 um
80+
[INFO CTS-0101] Average sink wire length 17.12 um
8181
[INFO CTS-0102] Path depth 2 - 2
8282
[INFO CTS-0207] Leaf load cells 1
8383
No differences found.

‎src/cts/test/simple_test_hier_out.vok‎

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5,18 +5,16 @@ module test_16_sinks (clk);
55
wire clknet_1_0__leaf_clk;
66
wire clknet_0_clk;
77

8-
INV_X1 clkload0 (.A(clknet_1_1__leaf_clk));
8+
INV_X1 clkload0 (.A(clknet_1_0__leaf_clk));
99
CLKBUF_X3 clkbuf_1_1__f_clk (.A(clknet_0_clk),
1010
.Z(clknet_1_1__leaf_clk));
1111
CLKBUF_X3 clkbuf_1_0__f_clk (.A(clknet_0_clk),
1212
.Z(clknet_1_0__leaf_clk));
1313
CLKBUF_X3 clkbuf_0_clk (.A(clk),
1414
.Z(clknet_0_clk));
15-
flop_pair U1 (.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
16-
flop_pair_U2 U2 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
17-
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
18-
flop_pair_U3 U3 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
19-
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
15+
flop_pair U1 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk));
16+
flop_pair_U2 U2 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk));
17+
flop_pair_U3 U3 (.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
2018
flop_pair_U4 U4 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
2119
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
2220
flop_pair_U5 U5 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
@@ -28,29 +26,25 @@ module test_16_sinks (clk);
2826
flop_pair_U8 U8 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
2927
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
3028
endmodule
31-
module flop_pair (clknet_1_0__leaf_clk_i);
32-
input clknet_1_0__leaf_clk_i;
29+
module flop_pair (clknet_1_1__leaf_clk_i);
30+
input clknet_1_1__leaf_clk_i;
3331

3432

35-
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
36-
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
33+
DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
34+
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
3735
endmodule
38-
module flop_pair_U2 (clknet_1_1__leaf_clk_i,
39-
clknet_1_0__leaf_clk_i);
36+
module flop_pair_U2 (clknet_1_1__leaf_clk_i);
4037
input clknet_1_1__leaf_clk_i;
41-
input clknet_1_0__leaf_clk_i;
4238

4339

4440
DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
45-
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
41+
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
4642
endmodule
47-
module flop_pair_U3 (clknet_1_1__leaf_clk_i,
48-
clknet_1_0__leaf_clk_i);
49-
input clknet_1_1__leaf_clk_i;
43+
module flop_pair_U3 (clknet_1_0__leaf_clk_i);
5044
input clknet_1_0__leaf_clk_i;
5145

5246

53-
DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
47+
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
5448
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
5549
endmodule
5650
module flop_pair_U4 (clknet_1_1__leaf_clk_i,
@@ -77,8 +71,8 @@ module flop_pair_U6 (clknet_1_1__leaf_clk_i,
7771
input clknet_1_0__leaf_clk_i;
7872

7973

80-
DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
81-
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
74+
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
75+
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
8276
endmodule
8377
module flop_pair_U7 (clknet_1_1__leaf_clk_i,
8478
clknet_1_0__leaf_clk_i);

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