cts: update regression tests that uses the apply_ndr cmd arg

Signed-off-by: Jonas Gava <[email protected]>

Author: jfgava

src/cts/README.md

@@ -62,6 +62,7 @@ clock_tree_synthesis
     [-sink_clustering_buffer]
     [-obstruction_aware]
     [-apply_ndr]
+    [-ndr_strategy strategy]
     [-insertion_delay]
     [-dont_use_dummy_load]
     [-sink_buffer_max_cap_derate derate_value]
@@ -92,7 +93,7 @@ clock_tree_synthesis
 | `-num_static_layers` | Set the number of static layers. The default value is `0`, and the allowed values are integers `[0, MAX_INT]`. |
 | `-sink_clustering_buffer` | Set the sink clustering buffer(s) to be used. |
 | `-obstruction_aware` | Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. This option may reduce legalizer displacement, leading to better latency, skew or timing QoR.  The default value is `False`, and the allowed values are bool. |
-| `-apply_ndr` | Applies 2X spacing non-default rule to all clock nets except leaf-level nets. The default value is `False`. |
+| `-apply_ndr` | Applies 2X spacing non-default rule to clock nets except leaf-level nets following some strategy. There are four strategy options: `none, root_only, half, full`. The default value is `root_only`. |
 | `-dont_use_dummy_load` | Don't apply dummy buffer or inverter cells at clock tree leaves to balance loads. The default values is `False`. |
 | `-sink_buffer_max_cap_derate` | Use this option to control automatic buffer selection. To favor strong(weak) drive strength buffers use a small(large) value.  The default value is `0.01`, meaning that buffers are selected by derating max cap limit by 0.01. The value of 1.0 means no derating of max cap limit.  |
 | `-delay_buffer_derate` | This option balances latencies between macro cells and registers by inserting delay buffers.  The default value is `1.0`, meaning all needed delay buffers are inserted.  A value of 0.5 means only half of necessary delay buffers are inserted.  A value of 0.0 means no insertion of delay buffers. |

src/cts/test/cts_aux.py

@@ -54,15 +54,14 @@ def clock_tree_synthesis(
     sink_clustering_levels=None,
     num_static_layers=None,
     sink_clustering_buffer=None,
-    apply_ndr=False,
+    apply_ndr=None,
 ):
     cts = design.getTritonCts()
     parms = cts.getParms()
 
     # Boolean
     parms.setSinkClustering(sink_clustering_enable)
     parms.setBalanceLevels(balance_levels)
-    parms.setApplyNDR(apply_ndr)
 
     if is_pos_int(sink_clustering_size):
         parms.setSinkClusteringSize(sink_clustering_size)
@@ -120,6 +119,9 @@ def clock_tree_synthesis(
     else:
         cts.setSinkBuffer("")
 
+    if apply_ndr != None:
+        parms.setApplyNDR(apply_ndr)
+
     if design.getBlock() == None:
         utl.error(utl.CTS, 604, "No design block found.")
 

src/cts/test/simple_test.py

@@ -17,7 +17,7 @@
     root_buf="CLKBUF_X3",
     buf_list="CLKBUF_X3",
     wire_unit=20,
-    apply_ndr=True,
+    apply_ndr="root_only",
 )
 
 cts_aux.report_cts(design)

src/cts/test/simple_test.tcl

@@ -10,7 +10,7 @@ set_wire_rc -clock -layer metal3
 clock_tree_synthesis -root_buf CLKBUF_X3 \
   -buf_list CLKBUF_X3 \
   -wire_unit 20 \
-  -apply_ndr
+  -apply_ndr root_only
 
 report_cts
 

src/cts/test/simple_test_hier.tcl

@@ -21,7 +21,7 @@ create_clock -period 5 clk
 
 set_wire_rc -clock -layer metal3
 
-clock_tree_synthesis -root_buf CLKBUF_X3 -buf_list CLKBUF_X3 -wire_unit 20 -apply_ndr
+clock_tree_synthesis -root_buf CLKBUF_X3 -buf_list CLKBUF_X3 -wire_unit 20 -apply_ndr root_only
 
 set verilog_file [make_result_file simple_test_hier_out.v]
 write_verilog $verilog_file

src/cts/test/twice.tcl

@@ -11,12 +11,12 @@ set_wire_rc -clock -layer metal3
 clock_tree_synthesis -root_buf CLKBUF_X3 \
   -buf_list CLKBUF_X3 \
   -wire_unit 20 \
-  -apply_ndr
+  -apply_ndr root_only
 
 clock_tree_synthesis -root_buf CLKBUF_X3 \
   -buf_list CLKBUF_X3 \
   -wire_unit 20 \
-  -apply_ndr
+  -apply_ndr root_only
 
 set def_file [make_result_file twice.def]
 write_def $def_file