Merge pull request #9174 from The-OpenROAD-Project-staging/dpl-bzl-fixes-seq

Fix dpl result difference in cmake vs bazel

Author: maliberty

src/cts/test/array.ok

@@ -128,11 +128,11 @@ Dummys used:
 [INFO RSZ-0048] Inserted 92 buffers in 41 nets.
 Placement Analysis
 ---------------------------------
-total displacement       3816.2 u
+total displacement       3812.8 u
 average displacement        1.2 u
 max displacement          140.5 u
 original HPWL          192614.2 u
-legalized HPWL         193656.0 u
+legalized HPWL         193657.1 u
 delta HPWL                    1 %
 
 Clock clk

src/cts/test/array_ins_delay.ok

@@ -118,11 +118,11 @@
 [INFO RSZ-0048] Inserted 92 buffers in 41 nets.
 Placement Analysis
 ---------------------------------
-total displacement       3816.2 u
+total displacement       3812.8 u
 average displacement        1.2 u
 max displacement          140.5 u
 original HPWL          192614.2 u
-legalized HPWL         193656.0 u
+legalized HPWL         193657.1 u
 delta HPWL                    1 %
 
 Clock clk

src/cts/test/array_no_blockages.ok

@@ -117,11 +117,11 @@
 [INFO RSZ-0048] Inserted 93 buffers in 42 nets.
 Placement Analysis
 ---------------------------------
-total displacement       3849.8 u
+total displacement       3848.2 u
 average displacement        1.2 u
 max displacement          141.1 u
 original HPWL          193578.0 u
-legalized HPWL         194591.1 u
+legalized HPWL         194590.6 u
 delta HPWL                    1 %
 
 Clock clk

src/cts/test/array_repair_clock_nets.ok

@@ -132,11 +132,11 @@ Dummys used:
 [INFO RSZ-0048] Inserted 5 buffers in 5 nets.
 Placement Analysis
 ---------------------------------
-total displacement       4103.0 u
+total displacement       4099.6 u
 average displacement        1.3 u
 max displacement          140.5 u
 original HPWL          189346.3 u
-legalized HPWL         190391.5 u
+legalized HPWL         190392.6 u
 delta HPWL                    1 %
 
 Clock clk

src/cts/test/gated_clock4.ok

@@ -38,12 +38,12 @@ Using 2 tracks default min distance between IO pins.
 [InitialPlace]  Iter: 5 conjugate gradient residual: 0.00000011 HPWL: 61445
 Placement Analysis
 ---------------------------------
-total displacement       6730.7 u
+total displacement       6732.7 u
 average displacement       23.8 u
-max displacement           35.5 u
+max displacement           35.6 u
 original HPWL               0.9 u
-legalized HPWL            388.7 u
-delta HPWL                44019 %
+legalized HPWL            393.7 u
+delta HPWL                44584 %
 
 [INFO CTS-0050] Root buffer is CLKBUF_X3.
 [INFO CTS-0051] Sink buffer is CLKBUF_X3.
@@ -67,8 +67,8 @@ delta HPWL                44019 %
 [INFO CTS-0030]  Number of static layers: 1.
 [INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
 [INFO CTS-0021]  Distance between buffers: 7 units (100 um).
-[INFO CTS-0023]  Original sink region: [(1003215, 1965350), (1006445, 1982150)].
-[INFO CTS-0024]  Normalized sink region: [(71.6582, 140.382), (71.8889, 141.582)].
+[INFO CTS-0023]  Original sink region: [(1003215, 1966190), (1006445, 1982990)].
+[INFO CTS-0024]  Normalized sink region: [(71.6582, 140.442), (71.8889, 141.642)].
 [INFO CTS-0025]     Width:  0.2307.
 [INFO CTS-0026]     Height: 1.2000.
  Level 1
@@ -231,7 +231,7 @@ delta HPWL                44019 %
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
 [INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
 [INFO CTS-0015]     Created 17 clock nets.
-[INFO CTS-0016]     Fanout distribution for the current clock = 4:1, 6:3, 7:3, 8:1, 9:4, 10:1, 11:1, 13:2..
+[INFO CTS-0016]     Fanout distribution for the current clock = 4:1, 6:4, 7:2, 8:1, 9:3, 10:2, 11:1, 12:1, 14:1..
 [INFO CTS-0017]     Max level of the clock tree: 4.
 [INFO CTS-0018]     Created 5 clock buffers.
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
@@ -249,7 +249,7 @@ delta HPWL                44019 %
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
 [INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
 [INFO CTS-0015]     Created 5 clock nets.
-[INFO CTS-0016]     Fanout distribution for the current clock = 7:1, 8:1, 10:1, 11:1..
+[INFO CTS-0016]     Fanout distribution for the current clock = 8:2, 10:2..
 [INFO CTS-0017]     Max level of the clock tree: 2.
 [INFO CTS-0018]     Created 5 clock buffers.
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
@@ -261,54 +261,54 @@ delta HPWL                44019 %
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
 [INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
 [INFO CTS-0015]     Created 5 clock nets.
-[INFO CTS-0016]     Fanout distribution for the current clock = 7:1, 8:1, 9:1, 12:1..
+[INFO CTS-0016]     Fanout distribution for the current clock = 6:1, 9:1, 10:1, 11:1..
 [INFO CTS-0017]     Max level of the clock tree: 2.
 [INFO CTS-0098] Clock net "clk"
 [INFO CTS-0099]  Sinks 4
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 27.29 um
+[INFO CTS-0101]  Average sink wire length 26.98 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "h1\/gclk5"
-[INFO CTS-0099]  Sinks 148
+[INFO CTS-0099]  Sinks 149
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 27.71 um
+[INFO CTS-0101]  Average sink wire length 27.56 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Dummy loads inserted 14
+[INFO CTS-0207]  Dummy loads inserted 15
 [INFO CTS-0098] Clock net "h1\/gclk2"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 19.75 um
+[INFO CTS-0101]  Average sink wire length 19.51 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0124] Clock net "gclk4"
 [INFO CTS-0125]  Sinks 1
 [INFO CTS-0098] Clock net "gclk4_regs"
-[INFO CTS-0099]  Sinks 39
+[INFO CTS-0099]  Sinks 38
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 20.43 um
+[INFO CTS-0101]  Average sink wire length 20.63 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Dummy loads inserted 3
+[INFO CTS-0207]  Dummy loads inserted 2
 [INFO CTS-0098] Clock net "gclk3"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 13.20 um
+[INFO CTS-0101]  Average sink wire length 13.38 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0098] Clock net "gclk1"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 17.13 um
+[INFO CTS-0101]  Average sink wire length 17.25 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0033] Balancing latency for clock core
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_0_core is inserted at (1005383 1975061)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_core is inserted at (1004321 1975143)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_core is inserted at (1004458 1962433)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_core is inserted at (1003836 1963891)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_core is inserted at (1005080 1978475)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_core is inserted at (1005080 1981975)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_core is inserted at (1005080 1985475)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_core is inserted at (1004458 1963273)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_core is inserted at (1003836 1964731)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_core is inserted at (1005080 1979315)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_core is inserted at (1005080 1982815)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_core is inserted at (1005080 1986315)
 [INFO CTS-0036]  inserted 7 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 7
 No differences found.