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malibertymaliberty
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Merge pull request #8124 from braydenlouie/grid-branch
ram: initial complete version
2 parents d300307 + 3879419 commit 346855b

29 files changed

+1978
-1
lines changed

‎.clang-tidy‎

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@@ -65,7 +65,7 @@ CheckOptions:
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# All modules but sta
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# Exclude build as there is too much noise from swig generated code
68-
HeaderFilterRegex: "(?!build/.*)/(ant|cts|dbSta|dft|dpl|drt|dst|est|exa|fin|gpl|grt|gui|ifp|mpl|odb|ord|pad|par|pdn|ppl|psm|rcx|rmp|rsz|stt|tap|upf|utl)/.*"
68+
HeaderFilterRegex: "(?!build/.*)/(ant|cgt|cts|cut|dbSta|dft|dpl|drt|dst|est|exa|fin|gpl|grt|gui|ifp|mpl|odb|ord|pad|par|pdn|ppl|psm|rcx|ram|rmp|rsz|stt|tap|upf|utl)/.*"
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# Not currently handling identifier naming
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# WarningsAsErrors: "*"

‎BUILD.bazel‎

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@@ -90,6 +90,7 @@ OPENROAD_LIBRARY_DEPS = [
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"//src/pdn",
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"//src/ppl",
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"//src/psm",
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"//src/ram",
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"//src/rcx",
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"//src/rcx:ui",
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"//src/rmp",

‎include/ord/OpenRoad.hh‎

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@@ -64,6 +64,10 @@ namespace fin {
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class Finale;
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}
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namespace ram {
68+
class RamGen;
69+
}
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namespace exa {
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class Example;
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}
@@ -156,6 +160,7 @@ class OpenRoad
156160
dbVerilogNetwork* getVerilogNetwork() { return verilog_network_; }
157161
dpl::Opendp* getOpendp() { return opendp_; }
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fin::Finale* getFinale() { return finale_; }
163+
ram::RamGen* getRamGen() { return ram_gen_; }
159164
tap::Tapcell* getTapcell() { return tapcell_; }
160165
mpl::MacroPlacer* getMacroPlacer() { return macro_placer_; }
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exa::Example* getExample() { return example_; }
@@ -255,6 +260,7 @@ class OpenRoad
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ppl::IOPlacer* ioPlacer_ = nullptr;
256261
dpl::Opendp* opendp_ = nullptr;
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fin::Finale* finale_ = nullptr;
263+
ram::RamGen* ram_gen_ = nullptr;
258264
mpl::MacroPlacer* macro_placer_ = nullptr;
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exa::Example* example_ = nullptr;
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grt::GlobalRouter* global_router_ = nullptr;

‎src/CMakeLists.txt‎

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@@ -263,6 +263,7 @@ add_subdirectory(gpl)
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add_subdirectory(dpl)
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add_subdirectory(exa)
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add_subdirectory(fin)
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add_subdirectory(ram)
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add_subdirectory(ppl)
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add_subdirectory(rmp)
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add_subdirectory(cgt)
@@ -326,6 +327,7 @@ target_link_libraries(openroad
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dpl
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exa
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fin
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ram
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rsz
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ppl
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stt
@@ -422,6 +424,7 @@ if (Python3_FOUND AND BUILD_PYTHON)
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cts_py
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drt_py
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fin_py
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# ram_py
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rcx_py
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rmp_py
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stt_py

‎src/OpenRoad.cc‎

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@@ -67,6 +67,8 @@
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#include "ppl/MakeIoplacer.h"
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#include "psm/MakePDNSim.hh"
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#include "psm/pdnsim.h"
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#include "ram/MakeRam.h"
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#include "ram/ram.h"
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#include "rcx/MakeOpenRCX.h"
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#include "rcx/ext.h"
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#include "rmp/MakeRestructure.h"
@@ -135,6 +137,7 @@ OpenRoad::~OpenRoad()
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delete replace_;
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delete pdnsim_;
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delete finale_;
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delete ram_gen_;
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delete antenna_checker_;
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odb::dbDatabase::destroy(db_);
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delete partitionMgr_;
@@ -220,6 +223,7 @@ void OpenRoad::init(Tcl_Interp* tcl_interp,
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opendp_,
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estimate_parasitics_);
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finale_ = new fin::Finale(db_, logger_);
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ram_gen_ = new ram::RamGen(getDbNetwork(), db_, logger_);
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restructure_ = new rmp::Restructure(
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logger_, sta_, db_, resizer_, estimate_parasitics_);
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clock_gating_ = new cgt::ClockGating(logger_, sta_);
@@ -253,6 +257,7 @@ void OpenRoad::init(Tcl_Interp* tcl_interp,
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utl::evalTclInit(tcl_interp, ord::ord_tcl_inits);
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utl::initLogger(tcl_interp);
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// GUI first so we can register our sink with the logger
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gui::initGui(tcl_interp, db_, sta_, logger_);
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odb::initOdb(tcl_interp);
@@ -264,6 +269,7 @@ void OpenRoad::init(Tcl_Interp* tcl_interp,
264269
gpl::initReplace(tcl_interp);
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dpl::initOpendp(tcl_interp);
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fin::initFinale(tcl_interp);
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ram::initRamGen(tcl_interp);
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grt::initTcl(tcl_interp);
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cts::initTritonCts(tcl_interp);
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tap::initTapcell(tcl_interp);

‎src/ram/.gitignore‎

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test/results
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*~

‎src/ram/BUILD‎

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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (c) 2025, The OpenROAD Authors
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load("@rules_cc//cc:cc_library.bzl", "cc_library")
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load("//bazel:python_wrap_cc.bzl", "python_wrap_cc")
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load("//bazel:tcl_encode_or.bzl", "tcl_encode")
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load("//bazel:tcl_wrap_cc.bzl", "tcl_wrap_cc")
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package(
10+
default_visibility = ["//:__subpackages__"],
11+
features = ["layering_check"],
12+
)
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cc_library(
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name = "ram",
16+
srcs = [
17+
"src/MakeRam.cpp",
18+
"src/layout.cpp",
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"src/layout.h",
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"src/ram.cpp",
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":swig",
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":tcl",
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],
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hdrs = [
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"include/ram/MakeRam.h",
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"include/ram/ram.h",
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],
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includes = [
29+
"include",
30+
],
31+
deps = [
32+
"//:ord",
33+
"//src/dbSta:dbNetwork",
34+
"//src/odb",
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"//src/sta:opensta_lib",
36+
"//src/utl",
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"@boost.stacktrace",
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"@tk_tcl//:tcl",
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],
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)
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tcl_encode(
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name = "tcl",
44+
srcs = [
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"src/ram.tcl",
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],
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char_array_name = "ram_tcl_inits",
48+
namespace = "ram",
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)
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tcl_wrap_cc(
52+
name = "swig",
53+
srcs = [
54+
"src/ram.i",
55+
"//:error_swig",
56+
],
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module = "ram",
58+
namespace_prefix = "ram",
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root_swig_src = "src/ram.i",
60+
swig_includes = [
61+
"src/ram/src",
62+
],
63+
deps = [
64+
"//src/odb:swig",
65+
],
66+
)
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68+
python_wrap_cc(
69+
name = "swig-py",
70+
srcs = [
71+
"include/ram/ram.h",
72+
"src/ram-py.i",
73+
"//:error_swig-py",
74+
],
75+
module = "ram_py",
76+
root_swig_src = "src/ram-py.i",
77+
swig_includes = [
78+
"include",
79+
],
80+
deps = [
81+
"//src/odb:swig-py",
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],
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)

‎src/ram/CMakeLists.txt‎

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###########################################################################
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## BSD 3-Clause License
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##
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## Copyright (c) 2023, Precision Innovations Inc.
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## All rights reserved.
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##
7+
## Redistribution and use in source and binary forms, with or without
8+
## modification, are permitted provided that the following conditions are met:
9+
##
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## * Redistributions of source code must retain the above copyright notice, this
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## list of conditions and the following disclaimer.
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##
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## * Redistributions in binary form must reproduce the above copyright notice,
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## this list of conditions and the following disclaimer in the documentation
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## and/or other materials provided with the distribution.
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##
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## * Neither the name of the copyright holder nor the names of its
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## contributors may be used to endorse or promote products derived from
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## this software without specific prior written permission.
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##
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## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24+
## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25+
## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26+
## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27+
## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28+
## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30+
## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31+
## POSSIBILITY OF SUCH DAMAGE.
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###########################################################################
33+
34+
include("openroad")
35+
36+
swig_lib(NAME ram
37+
NAMESPACE ram
38+
I_FILE src/ram.i
39+
SCRIPTS src/ram.tcl
40+
)
41+
42+
target_sources(ram
43+
PRIVATE
44+
src/ram.cpp
45+
src/layout.cpp
46+
src/MakeRam.cpp
47+
)
48+
49+
target_include_directories(ram
50+
PUBLIC
51+
include
52+
)
53+
54+
target_link_libraries(ram
55+
PRIVATE
56+
odb
57+
dbSta
58+
OpenSTA
59+
)
60+
61+
messages(
62+
TARGET ram
63+
)
64+
65+
#if (Python3_FOUND AND BUILD_PYTHON)
66+
# swig_lib(NAME ram_py
67+
# NAMESPACE ram
68+
# LANGUAGE python
69+
# I_FILE src/ram-py.i
70+
# SWIG_INCLUDES ${PROJECT_SOURCE_DIR}/include/ram
71+
# SCRIPTS ${CMAKE_CURRENT_BINARY_DIR}/ram_py.py
72+
# )
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#
74+
# target_link_libraries(ram_py
75+
# PUBLIC
76+
# ram
77+
# odb
78+
# )
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#
80+
#endif()
81+
82+
add_subdirectory(test)

‎src/ram/include/ram/MakeRam.h‎

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// SPDX-License-Identifier: BSD-3-Clause
2+
// Copyright (c) 2024-2025, The OpenROAD Authors
3+
4+
#pragma once
5+
6+
#include <tcl.h>
7+
8+
namespace ram {
9+
10+
void initRamGen(Tcl_Interp* tcl_interp);
11+
12+
} // namespace ram

‎src/ram/include/ram/ram.h‎

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// SPDX-License-Identifier: BSD-3-Clause
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// Copyright (c) 2024-2025, The OpenROAD Authors
3+
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#pragma once
5+
6+
#include <functional>
7+
#include <memory>
8+
9+
#include "odb/db.h"
10+
11+
namespace odb {
12+
class dbMaster;
13+
}
14+
15+
namespace sta {
16+
class dbNetwork;
17+
class LibertyPort;
18+
} // namespace sta
19+
20+
namespace utl {
21+
class Logger;
22+
}
23+
24+
namespace ram {
25+
26+
using utl::Logger;
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28+
////////////////////////////////////////////////////////////////
29+
class Cell;
30+
class Layout;
31+
class Grid;
32+
33+
class RamGen
34+
{
35+
public:
36+
RamGen(sta::dbNetwork* network, odb::dbDatabase* db, Logger* logger);
37+
~RamGen() = default;
38+
39+
void generate(int bytes_per_word,
40+
int word_count,
41+
int read_ports,
42+
odb::dbMaster* storage_cell,
43+
odb::dbMaster* tristate_cell,
44+
odb::dbMaster* inv_cell);
45+
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private:
47+
void findMasters();
48+
odb::dbMaster* findMaster(const std::function<bool(sta::LibertyPort*)>& match,
49+
const char* name);
50+
odb::dbNet* makeNet(const std::string& prefix, const std::string& name);
51+
odb::dbInst* makeInst(
52+
Layout* layout,
53+
const std::string& prefix,
54+
const std::string& name,
55+
odb::dbMaster* master,
56+
const std::vector<std::pair<std::string, odb::dbNet*>>& connections);
57+
odb::dbInst* makeCellInst(
58+
Cell* cell,
59+
const std::string& prefix,
60+
const std::string& name,
61+
odb::dbMaster* master,
62+
const std::vector<std::pair<std::string, odb::dbNet*>>& connections);
63+
std::unique_ptr<Cell> makeCellBit(const std::string& prefix,
64+
int read_ports,
65+
odb::dbNet* clock,
66+
std::vector<odb::dbNet*>& select,
67+
odb::dbNet* data_input,
68+
std::vector<odb::dbNet*>& data_output);
69+
void makeCellByte(
70+
Grid& ram_grid,
71+
int byte_number,
72+
const std::string& prefix,
73+
int read_ports,
74+
odb::dbNet* clock,
75+
odb::dbNet* write_enable,
76+
const std::vector<odb::dbNet*>& selects,
77+
const std::array<odb::dbNet*, 8>& data_input,
78+
const std::vector<std::array<odb::dbBTerm*, 8>>& data_output);
79+
80+
odb::dbBTerm* makeBTerm(const std::string& name, odb::dbIoType io_type);
81+
82+
std::unique_ptr<Cell> makeDecoder(const std::string& prefix,
83+
int num_word,
84+
int read_ports,
85+
const std::vector<odb::dbNet*>& selects,
86+
const std::vector<odb::dbNet*>& addr_nets);
87+
88+
std::vector<odb::dbNet*> selectNets(const std::string& prefix,
89+
int read_ports);
90+
91+
sta::dbNetwork* network_;
92+
odb::dbDatabase* db_;
93+
odb::dbBlock* block_;
94+
Logger* logger_;
95+
96+
odb::dbMaster* storage_cell_;
97+
odb::dbMaster* tristate_cell_;
98+
odb::dbMaster* inv_cell_;
99+
odb::dbMaster* and2_cell_;
100+
odb::dbMaster* clock_gate_cell_;
101+
odb::dbMaster* buffer_cell_;
102+
};
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} // namespace ram

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