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malibertymaliberty
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Merge pull request #8816 from gadfort/pad-add-left
pad: add linear mode to placement
2 parents f22f811 + 86e3aa1 commit 369e8f0

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9 files changed

+96
-76
lines changed

9 files changed

+96
-76
lines changed

‎src/pad/README.md‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -228,7 +228,7 @@ place_pads
228228
| Switch Name | Description |
229229
| ----- | ----- |
230230
| `-row` | Name of the row to place the pad into, examples include: `IO_NORTH`, `IO_SOUTH`, `IO_WEST`, `IO_EAST`, `IO_NORTH_0`, `IO_NORTH_1`. |
231-
| `-mode` | Select the mode to use during pad placement, choices are `bump_aligned` and `uniform`. Default will select `bump_aligned` if possible, otherwise fallback to `uniform`. |
231+
| `-mode` | Select the mode to use during pad placement, choices are `bump_aligned`, `linear`, and `uniform`. Default will select `bump_aligned` if possible, otherwise fallback to `uniform`. |
232232
| `pads` | Name of the instances in the order they should be placed (left to right for `IO_SOUTH` and `IO_NORTH` and bottom to top for `IO_WEST` and `IO_EAST`). |
233233

234234
#### Modes
@@ -241,6 +241,10 @@ In `bump_aligned` mode, the pads will be clustered near their assigned bumps to
241241

242242
<img src="./doc/image/mode_bump_aligned.png" width=450px>
243243

244+
In `linear` mode, the pads will be place starting from the bottom or left of the row next to eachother.
245+
246+
<img src="./doc/image/mode_linear.png" width=450px>
247+
244248
### Placing Pads Manually
245249

246250
To place a pad into the pad ring.

‎src/pad/doc/image/mode_linear.png‎

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‎src/pad/include/pad/ICeWall.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,8 @@ enum class PlacementStrategy
3030
{
3131
DEFAULT,
3232
BUMP_ALIGNED,
33-
UNIFORM
33+
UNIFORM,
34+
LINEAR
3435
};
3536

3637
class ICeWall

‎src/pad/src/ICeWall.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -746,6 +746,10 @@ void ICeWall::placePads(const std::vector<odb::dbInst*>& insts,
746746
placer = std::move(bump_placer);
747747
break;
748748
}
749+
case PlacementStrategy::LINEAR:
750+
placer = std::make_unique<UniformPadPlacer>(
751+
logger_, block, insts, row_dir, row, 0);
752+
break;
749753
case PlacementStrategy::UNIFORM:
750754
case PlacementStrategy::DEFAULT:
751755
placer = std::make_unique<UniformPadPlacer>(

‎src/pad/src/PadPlacer.cpp‎

Lines changed: 16 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ void PadPlacer::populateInstWidths()
4545
master->getPlacementBoundary(inst_bbox);
4646
xform.apply(inst_bbox);
4747

48-
switch (getRowDirection()) {
48+
switch (getRowEdge()) {
4949
case odb::Direction2D::North:
5050
case odb::Direction2D::South:
5151
inst_widths_[inst] = inst_bbox.dx();
@@ -63,7 +63,7 @@ int PadPlacer::getRowStart() const
6363
const odb::Rect row_bbox = getRow()->getBBox();
6464

6565
int row_start = 0;
66-
switch (getRowDirection()) {
66+
switch (getRowEdge()) {
6767
case odb::Direction2D::North:
6868
case odb::Direction2D::South:
6969
row_start = row_bbox.xMin();
@@ -82,7 +82,7 @@ int PadPlacer::getRowEnd() const
8282
const odb::Rect row_bbox = getRow()->getBBox();
8383

8484
int row_end = 0;
85-
switch (getRowDirection()) {
85+
switch (getRowEdge()) {
8686
case odb::Direction2D::North:
8787
case odb::Direction2D::South:
8888
row_end = row_bbox.xMax();
@@ -101,7 +101,7 @@ int PadPlacer::getRowWidth() const
101101
const odb::Rect row_bbox = getRow()->getBBox();
102102

103103
int row_width = 0;
104-
switch (getRowDirection()) {
104+
switch (getRowEdge()) {
105105
case odb::Direction2D::North:
106106
case odb::Direction2D::South:
107107
row_width = row_bbox.dx();
@@ -398,8 +398,9 @@ UniformPadPlacer::UniformPadPlacer(utl::Logger* logger,
398398
odb::dbBlock* block,
399399
const std::vector<odb::dbInst*>& insts,
400400
const odb::Direction2D::Value& edge,
401-
odb::dbRow* row)
402-
: PadPlacer(logger, block, insts, edge, row)
401+
odb::dbRow* row,
402+
std::optional<int> max_spacing)
403+
: PadPlacer(logger, block, insts, edge, row), max_spacing_(max_spacing)
403404
{
404405
}
405406

@@ -408,9 +409,13 @@ void UniformPadPlacer::place()
408409
const bool gui_debug
409410
= getLogger()->debugCheck(utl::PAD, "Place", 1) && gui::Gui::enabled();
410411

411-
const float initial_target_spacing
412+
float initial_target_spacing
412413
= static_cast<float>(getRowWidth() - getTotalInstWidths())
413414
/ (getInsts().size() + 1);
415+
if (max_spacing_) {
416+
initial_target_spacing
417+
= std::min<float>(*max_spacing_, initial_target_spacing);
418+
}
414419
const int site_width = std::min(getRow()->getSite()->getWidth(),
415420
getRow()->getSite()->getHeight());
416421
const int target_spacing
@@ -518,7 +523,7 @@ void BumpAlignedPadPlacer::place()
518523
std::map<odb::dbInst*, int> inst_pos;
519524
if (!min_terms.empty()) {
520525
int group_center = 0;
521-
switch (getRowDirection()) {
526+
switch (getRowEdge()) {
522527
case odb::Direction2D::North:
523528
case odb::Direction2D::South:
524529
group_center = min_terms.at(inst)->getBBox().xCenter();
@@ -592,7 +597,7 @@ int64_t BumpAlignedPadPlacer::computePadBumpDistance(odb::dbInst* inst,
592597
const odb::Point row_center = getRow()->getBBox().center();
593598
const odb::Point center = bump->getBBox().center();
594599

595-
switch (getRowDirection()) {
600+
switch (getRowEdge()) {
596601
case odb::Direction2D::North:
597602
case odb::Direction2D::South:
598603
return odb::Point::squaredDistance(
@@ -639,7 +644,7 @@ BumpAlignedPadPlacer::getBumpAlignmentGroup(
639644
// no longer the first pad in group, check if bumps are in same
640645
// column/row
641646
bool keep = true;
642-
switch (getRowDirection()) {
647+
switch (getRowEdge()) {
643648
case odb::Direction2D::North:
644649
case odb::Direction2D::South:
645650
keep = min_terms[inst]->getBBox().xCenter()
@@ -713,7 +718,7 @@ void BumpAlignedPadPlacer::performPadFlip(odb::dbInst* inst) const
713718

714719
// try flipping pad
715720
inst->setPlacementStatus(odb::dbPlacementStatus::PLACED);
716-
switch (getRowDirection()) {
721+
switch (getRowEdge()) {
717722
case odb::Direction2D::North:
718723
case odb::Direction2D::South:
719724
inst->setLocationOrient(start_orient.flipY());

‎src/pad/src/PadPlacer.h‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ class PadPlacer
4444
utl::Logger* getLogger() const { return logger_; }
4545
odb::dbBlock* getBlock() const { return block_; }
4646
odb::dbRow* getRow() const { return row_; }
47-
const odb::Direction2D::Value& getRowDirection() const { return edge_; }
47+
const odb::Direction2D::Value& getRowEdge() const { return edge_; }
4848
const std::vector<odb::dbInst*>& getInsts() const { return insts_; }
4949

5050
int getRowStart() const;
@@ -120,10 +120,14 @@ class UniformPadPlacer : public PadPlacer
120120
odb::dbBlock* block,
121121
const std::vector<odb::dbInst*>& insts,
122122
const odb::Direction2D::Value& edge,
123-
odb::dbRow* row);
123+
odb::dbRow* row,
124+
std::optional<int> max_spacing = {});
124125
~UniformPadPlacer() override = default;
125126

126127
void place() override;
128+
129+
private:
130+
std::optional<int> max_spacing_;
127131
};
128132

129133
class BumpAlignedPadPlacer : public PadPlacer

‎src/pad/src/pad.i‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,8 @@ utl::Logger* getLogger();
3232
$1 = pad::PlacementStrategy::BUMP_ALIGNED;
3333
} else if (strcasecmp(str, "uniform") == 0) {
3434
$1 = pad::PlacementStrategy::UNIFORM;
35+
} else if (strcasecmp(str, "linear") == 0) {
36+
$1 = pad::PlacementStrategy::LINEAR;
3537
} else if (strcasecmp(str, "default") == 0) {
3638
$1 = pad::PlacementStrategy::DEFAULT;
3739
} else {

‎src/pad/test/place_pads_bumps_strategy.defok‎

Lines changed: 60 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -309,35 +309,35 @@ COMPONENTS 543 ;
309309
- BUMP_9_6 DUMMY_BUMP + FIXED ( 3300000 2350000 ) N ;
310310
- BUMP_9_7 DUMMY_BUMP + FIXED ( 3300000 2670000 ) N ;
311311
- BUMP_9_9 DUMMY_BUMP + FIXED ( 3300000 3310000 ) N ;
312-
- u_bsg_tag_clk_i PADCELL_SIG_H + FIXED ( 5690000 3076000 ) W ;
312+
- u_bsg_tag_clk_i PADCELL_SIG_H + FIXED ( 5690000 1860000 ) W ;
313313
- u_bsg_tag_clk_o PADCELL_SIG_H + FIXED ( 30000 3826000 ) FW ;
314-
- u_bsg_tag_data_i PADCELL_SIG_H + FIXED ( 5690000 3340000 ) W ;
314+
- u_bsg_tag_data_i PADCELL_SIG_H + FIXED ( 5690000 2010000 ) W ;
315315
- u_bsg_tag_data_o PADCELL_SIG_H + FIXED ( 30000 3626000 ) FW ;
316-
- u_bsg_tag_en_i PADCELL_SIG_H + FIXED ( 5690000 3428000 ) W ;
316+
- u_bsg_tag_en_i PADCELL_SIG_H + FIXED ( 5690000 2060000 ) W ;
317317
- u_ci2_0_o PADCELL_SIG_V + FIXED ( 3940000 5690000 ) FS ;
318318
- u_ci2_1_o PADCELL_SIG_V + FIXED ( 3990000 5690000 ) FS ;
319319
- u_ci2_2_o PADCELL_SIG_V + FIXED ( 4206000 5690000 ) FS ;
320320
- u_ci2_3_o PADCELL_SIG_V + FIXED ( 4256000 5690000 ) FS ;
321321
- u_ci2_4_o PADCELL_SIG_V + FIXED ( 4306000 5690000 ) FS ;
322322
- u_ci2_5_o PADCELL_SIG_V + FIXED ( 4920000 5690000 ) FS ;
323323
- u_ci2_6_o PADCELL_SIG_V + FIXED ( 5240000 5690000 ) FS ;
324-
- u_ci2_7_o PADCELL_SIG_V + FIXED ( 5690000 5540000 ) W ;
325-
- u_ci2_8_o PADCELL_SIG_V + FIXED ( 5690000 5452000 ) W ;
324+
- u_ci2_7_o PADCELL_SIG_V + FIXED ( 5690000 3260000 ) W ;
325+
- u_ci2_8_o PADCELL_SIG_V + FIXED ( 5690000 3210000 ) W ;
326326
- u_ci2_clk_o PADCELL_SIG_V + FIXED ( 4356000 5690000 ) FS ;
327327
- u_ci2_tkn_i PADCELL_SIG_V + FIXED ( 4576000 5690000 ) FS ;
328328
- u_ci2_v_o PADCELL_SIG_V + FIXED ( 4626000 5690000 ) FS ;
329-
- u_ci_0_i PADCELL_SIG_H + FIXED ( 5690000 5364000 ) W ;
330-
- u_ci_1_i PADCELL_SIG_H + FIXED ( 5690000 5100000 ) W ;
331-
- u_ci_2_i PADCELL_SIG_H + FIXED ( 5690000 4836000 ) W ;
332-
- u_ci_3_i PADCELL_SIG_H + FIXED ( 5690000 4748000 ) W ;
333-
- u_ci_4_i PADCELL_SIG_H + FIXED ( 5690000 4660000 ) W ;
334-
- u_ci_5_i PADCELL_SIG_H + FIXED ( 5690000 4132000 ) W ;
335-
- u_ci_6_i PADCELL_SIG_H + FIXED ( 5690000 4044000 ) W ;
336-
- u_ci_7_i PADCELL_SIG_H + FIXED ( 5690000 3780000 ) W ;
337-
- u_ci_8_i PADCELL_SIG_H + FIXED ( 5690000 3516000 ) W ;
338-
- u_ci_clk_i PADCELL_SIG_H + FIXED ( 5690000 4572000 ) W ;
339-
- u_ci_tkn_o PADCELL_SIG_H + FIXED ( 5690000 4308000 ) W ;
340-
- u_ci_v_i PADCELL_SIG_H + FIXED ( 5690000 4220000 ) W ;
329+
- u_ci_0_i PADCELL_SIG_H + FIXED ( 5690000 3160000 ) W ;
330+
- u_ci_1_i PADCELL_SIG_H + FIXED ( 5690000 3010000 ) W ;
331+
- u_ci_2_i PADCELL_SIG_H + FIXED ( 5690000 2860000 ) W ;
332+
- u_ci_3_i PADCELL_SIG_H + FIXED ( 5690000 2810000 ) W ;
333+
- u_ci_4_i PADCELL_SIG_H + FIXED ( 5690000 2760000 ) W ;
334+
- u_ci_5_i PADCELL_SIG_H + FIXED ( 5690000 2460000 ) W ;
335+
- u_ci_6_i PADCELL_SIG_H + FIXED ( 5690000 2410000 ) W ;
336+
- u_ci_7_i PADCELL_SIG_H + FIXED ( 5690000 2260000 ) W ;
337+
- u_ci_8_i PADCELL_SIG_H + FIXED ( 5690000 2110000 ) W ;
338+
- u_ci_clk_i PADCELL_SIG_H + FIXED ( 5690000 2710000 ) W ;
339+
- u_ci_tkn_o PADCELL_SIG_H + FIXED ( 5690000 2560000 ) W ;
340+
- u_ci_v_i PADCELL_SIG_H + FIXED ( 5690000 2510000 ) W ;
341341
- u_clk_A_i PADCELL_SIG_V + FIXED ( 2686000 5690000 ) FS ;
342342
- u_clk_B_i PADCELL_SIG_V + FIXED ( 3000000 5690000 ) FS ;
343343
- u_clk_C_i PADCELL_SIG_V + FIXED ( 3100000 5690000 ) FS ;
@@ -395,32 +395,32 @@ COMPONENTS 543 ;
395395
- u_ddr_dm_0_o PADCELL_SIG_H + FIXED ( 30000 2666000 ) FW ;
396396
- u_ddr_dm_1_o PADCELL_SIG_V + FIXED ( 352000 30000 ) N ;
397397
- u_ddr_dm_2_o PADCELL_SIG_V + FIXED ( 5412000 30000 ) N ;
398-
- u_ddr_dm_3_o PADCELL_SIG_H + FIXED ( 5690000 2988000 ) W ;
398+
- u_ddr_dm_3_o PADCELL_SIG_H + FIXED ( 5690000 1810000 ) W ;
399399
- u_ddr_dq_0_io PADCELL_SIG_H + FIXED ( 30000 2866000 ) FW ;
400400
- u_ddr_dq_10_io PADCELL_SIG_H + FIXED ( 30000 1680000 ) FW ;
401401
- u_ddr_dq_11_io PADCELL_SIG_H + FIXED ( 30000 2026000 ) FW ;
402402
- u_ddr_dq_12_io PADCELL_SIG_H + FIXED ( 30000 2076000 ) FW ;
403403
- u_ddr_dq_13_io PADCELL_SIG_H + FIXED ( 30000 2226000 ) FW ;
404404
- u_ddr_dq_14_io PADCELL_SIG_H + FIXED ( 30000 2320000 ) FW ;
405405
- u_ddr_dq_15_io PADCELL_SIG_H + FIXED ( 30000 2370000 ) FW ;
406-
- u_ddr_dq_16_io PADCELL_SIG_H + FIXED ( 5690000 1316000 ) W ;
407-
- u_ddr_dq_17_io PADCELL_SIG_H + FIXED ( 5690000 1228000 ) W ;
408-
- u_ddr_dq_18_io PADCELL_SIG_H + FIXED ( 5690000 1140000 ) W ;
409-
- u_ddr_dq_19_io PADCELL_SIG_H + FIXED ( 5690000 1052000 ) W ;
406+
- u_ddr_dq_16_io PADCELL_SIG_H + FIXED ( 5690000 860000 ) W ;
407+
- u_ddr_dq_17_io PADCELL_SIG_H + FIXED ( 5690000 810000 ) W ;
408+
- u_ddr_dq_18_io PADCELL_SIG_H + FIXED ( 5690000 760000 ) W ;
409+
- u_ddr_dq_19_io PADCELL_SIG_H + FIXED ( 5690000 710000 ) W ;
410410
- u_ddr_dq_1_io PADCELL_SIG_H + FIXED ( 30000 3010000 ) FW ;
411-
- u_ddr_dq_20_io PADCELL_SIG_H + FIXED ( 5690000 788000 ) W ;
412-
- u_ddr_dq_21_io PADCELL_SIG_H + FIXED ( 5690000 524000 ) W ;
413-
- u_ddr_dq_22_io PADCELL_SIG_H + FIXED ( 5690000 436000 ) W ;
414-
- u_ddr_dq_23_io PADCELL_SIG_H + FIXED ( 5690000 348000 ) W ;
415-
- u_ddr_dq_24_io PADCELL_SIG_H + FIXED ( 5690000 2548000 ) W ;
416-
- u_ddr_dq_25_io PADCELL_SIG_H + FIXED ( 5690000 2460000 ) W ;
417-
- u_ddr_dq_26_io PADCELL_SIG_H + FIXED ( 5690000 2372000 ) W ;
418-
- u_ddr_dq_27_io PADCELL_SIG_H + FIXED ( 5690000 2108000 ) W ;
419-
- u_ddr_dq_28_io PADCELL_SIG_H + FIXED ( 5690000 1844000 ) W ;
420-
- u_ddr_dq_29_io PADCELL_SIG_H + FIXED ( 5690000 1756000 ) W ;
411+
- u_ddr_dq_20_io PADCELL_SIG_H + FIXED ( 5690000 560000 ) W ;
412+
- u_ddr_dq_21_io PADCELL_SIG_H + FIXED ( 5690000 410000 ) W ;
413+
- u_ddr_dq_22_io PADCELL_SIG_H + FIXED ( 5690000 360000 ) W ;
414+
- u_ddr_dq_23_io PADCELL_SIG_H + FIXED ( 5690000 310000 ) W ;
415+
- u_ddr_dq_24_io PADCELL_SIG_H + FIXED ( 5690000 1560000 ) W ;
416+
- u_ddr_dq_25_io PADCELL_SIG_H + FIXED ( 5690000 1510000 ) W ;
417+
- u_ddr_dq_26_io PADCELL_SIG_H + FIXED ( 5690000 1460000 ) W ;
418+
- u_ddr_dq_27_io PADCELL_SIG_H + FIXED ( 5690000 1310000 ) W ;
419+
- u_ddr_dq_28_io PADCELL_SIG_H + FIXED ( 5690000 1160000 ) W ;
420+
- u_ddr_dq_29_io PADCELL_SIG_H + FIXED ( 5690000 1110000 ) W ;
421421
- u_ddr_dq_2_io PADCELL_SIG_H + FIXED ( 30000 3160000 ) FW ;
422-
- u_ddr_dq_30_io PADCELL_SIG_H + FIXED ( 5690000 1668000 ) W ;
423-
- u_ddr_dq_31_io PADCELL_SIG_H + FIXED ( 5690000 1580000 ) W ;
422+
- u_ddr_dq_30_io PADCELL_SIG_H + FIXED ( 5690000 1060000 ) W ;
423+
- u_ddr_dq_31_io PADCELL_SIG_H + FIXED ( 5690000 1010000 ) W ;
424424
- u_ddr_dq_3_io PADCELL_SIG_H + FIXED ( 30000 3210000 ) FW ;
425425
- u_ddr_dq_4_io PADCELL_SIG_H + FIXED ( 30000 3306000 ) FW ;
426426
- u_ddr_dq_5_io PADCELL_SIG_H + FIXED ( 30000 3356000 ) FW ;
@@ -431,11 +431,11 @@ COMPONENTS 543 ;
431431
- u_ddr_dqs_n_0_io PADCELL_SIG_H + FIXED ( 30000 2716000 ) FW ;
432432
- u_ddr_dqs_n_1_io PADCELL_SIG_V + FIXED ( 444000 30000 ) N ;
433433
- u_ddr_dqs_n_2_io PADCELL_SIG_V + FIXED ( 5228000 30000 ) N ;
434-
- u_ddr_dqs_n_3_io PADCELL_SIG_H + FIXED ( 5690000 2812000 ) W ;
434+
- u_ddr_dqs_n_3_io PADCELL_SIG_H + FIXED ( 5690000 1710000 ) W ;
435435
- u_ddr_dqs_p_0_io PADCELL_SIG_H + FIXED ( 30000 2420000 ) FW ;
436436
- u_ddr_dqs_p_1_io PADCELL_SIG_V + FIXED ( 628000 30000 ) N ;
437437
- u_ddr_dqs_p_2_io PADCELL_SIG_V + FIXED ( 5320000 30000 ) N ;
438-
- u_ddr_dqs_p_3_io PADCELL_SIG_H + FIXED ( 5690000 2900000 ) W ;
438+
- u_ddr_dqs_p_3_io PADCELL_SIG_H + FIXED ( 5690000 1760000 ) W ;
439439
- u_ddr_odt_o PADCELL_SIG_V + FIXED ( 3848000 30000 ) N ;
440440
- u_ddr_ras_n_o PADCELL_SIG_V + FIXED ( 4400000 30000 ) N ;
441441
- u_ddr_reset_n_o PADCELL_SIG_V + FIXED ( 3940000 30000 ) N ;
@@ -445,13 +445,13 @@ COMPONENTS 543 ;
445445
- u_sel_1_i PADCELL_SIG_V + FIXED ( 3640000 5690000 ) FS ;
446446
- u_sel_2_i PADCELL_SIG_V + FIXED ( 3790000 5690000 ) FS ;
447447
- u_v18_1 PADCELL_VDDIO_V + FIXED ( 1180000 30000 ) N ;
448-
- u_v18_10 PADCELL_VDDIO_H + FIXED ( 5690000 1492000 ) W ;
449-
- u_v18_11 PADCELL_VDDIO_H + FIXED ( 5690000 2020000 ) W ;
450-
- u_v18_12 PADCELL_VDDIO_H + FIXED ( 5690000 2724000 ) W ;
451-
- u_v18_13 PADCELL_VDDIO_H + FIXED ( 5690000 3252000 ) W ;
452-
- u_v18_14 PADCELL_VDDIO_H + FIXED ( 5690000 3956000 ) W ;
453-
- u_v18_15 PADCELL_VDDIO_H + FIXED ( 5690000 4484000 ) W ;
454-
- u_v18_16 PADCELL_VDDIO_H + FIXED ( 5690000 5012000 ) W ;
448+
- u_v18_10 PADCELL_VDDIO_H + FIXED ( 5690000 960000 ) W ;
449+
- u_v18_11 PADCELL_VDDIO_H + FIXED ( 5690000 1260000 ) W ;
450+
- u_v18_12 PADCELL_VDDIO_H + FIXED ( 5690000 1660000 ) W ;
451+
- u_v18_13 PADCELL_VDDIO_H + FIXED ( 5690000 1960000 ) W ;
452+
- u_v18_14 PADCELL_VDDIO_H + FIXED ( 5690000 2360000 ) W ;
453+
- u_v18_15 PADCELL_VDDIO_H + FIXED ( 5690000 2660000 ) W ;
454+
- u_v18_16 PADCELL_VDDIO_H + FIXED ( 5690000 2960000 ) W ;
455455
- u_v18_17 PADCELL_VDDIO_V + FIXED ( 5290000 5690000 ) FS ;
456456
- u_v18_18 PADCELL_VDDIO_V + FIXED ( 4406000 5690000 ) FS ;
457457
- u_v18_19 PADCELL_VDDIO_V + FIXED ( 4090000 5690000 ) FS ;
@@ -475,7 +475,7 @@ COMPONENTS 543 ;
475475
- u_v18_6 PADCELL_VDDIO_V + FIXED ( 4308000 30000 ) N ;
476476
- u_v18_7 PADCELL_VDDIO_V + FIXED ( 4860000 30000 ) N ;
477477
- u_v18_8 PADCELL_VDDIO_V + FIXED ( 5596000 30000 ) N ;
478-
- u_v18_9 PADCELL_VDDIO_H + FIXED ( 5690000 964000 ) W ;
478+
- u_v18_9 PADCELL_VDDIO_H + FIXED ( 5690000 660000 ) W ;
479479
- u_vdd_1 PADCELL_VDD_V + FIXED ( 2008000 30000 ) N ;
480480
- u_vdd_10 PADCELL_VDD_H + FIXED ( 2636000 5690000 ) FS ;
481481
- u_vdd_11 PADCELL_VDD_H + FIXED ( 1526000 5690000 ) FS ;
@@ -502,10 +502,10 @@ COMPONENTS 543 ;
502502
- u_vdd_30 PADCELL_VDD_H ;
503503
- u_vdd_31 PADCELL_VDD_H ;
504504
- u_vdd_32 PADCELL_VDD_H ;
505-
- u_vdd_4 PADCELL_VDD_V + FIXED ( 5690000 612000 ) W ;
506-
- u_vdd_5 PADCELL_VDD_V + FIXED ( 5690000 2196000 ) W ;
507-
- u_vdd_6 PADCELL_VDD_V + FIXED ( 5690000 3604000 ) W ;
508-
- u_vdd_7 PADCELL_VDD_V + FIXED ( 5690000 5188000 ) W ;
505+
- u_vdd_4 PADCELL_VDD_V + FIXED ( 5690000 460000 ) W ;
506+
- u_vdd_5 PADCELL_VDD_V + FIXED ( 5690000 1360000 ) W ;
507+
- u_vdd_6 PADCELL_VDD_V + FIXED ( 5690000 2160000 ) W ;
508+
- u_vdd_7 PADCELL_VDD_V + FIXED ( 5690000 3060000 ) W ;
509509
- u_vdd_8 PADCELL_VDD_H + FIXED ( 4726000 5690000 ) FS ;
510510
- u_vdd_9 PADCELL_VDD_H + FIXED ( 3890000 5690000 ) FS ;
511511
- u_vdd_pll PADCELL_VDD_V + FIXED ( 3250000 5690000 ) FS ;
@@ -536,22 +536,22 @@ COMPONENTS 543 ;
536536
- u_vss_30 PADCELL_VSS_H ;
537537
- u_vss_31 PADCELL_VSS_H ;
538538
- u_vss_32 PADCELL_VSS_H ;
539-
- u_vss_4 PADCELL_VSS_V + FIXED ( 5690000 700000 ) W ;
540-
- u_vss_5 PADCELL_VSS_V + FIXED ( 5690000 2284000 ) W ;
541-
- u_vss_6 PADCELL_VSS_V + FIXED ( 5690000 3692000 ) W ;
542-
- u_vss_7 PADCELL_VSS_V + FIXED ( 5690000 5276000 ) W ;
539+
- u_vss_4 PADCELL_VSS_V + FIXED ( 5690000 510000 ) W ;
540+
- u_vss_5 PADCELL_VSS_V + FIXED ( 5690000 1410000 ) W ;
541+
- u_vss_6 PADCELL_VSS_V + FIXED ( 5690000 2210000 ) W ;
542+
- u_vss_7 PADCELL_VSS_V + FIXED ( 5690000 3110000 ) W ;
543543
- u_vss_8 PADCELL_VSS_H + FIXED ( 4676000 5690000 ) FS ;
544544
- u_vss_9 PADCELL_VSS_H + FIXED ( 3840000 5690000 ) FS ;
545545
- u_vss_pll PADCELL_VSS_V + FIXED ( 3370000 5690000 ) FS ;
546546
- u_vzz_0 PADCELL_VSSIO_V + FIXED ( 536000 30000 ) N ;
547547
- u_vzz_1 PADCELL_VSSIO_V + FIXED ( 1088000 30000 ) N ;
548-
- u_vzz_10 PADCELL_VSSIO_H + FIXED ( 5690000 1404000 ) W ;
549-
- u_vzz_11 PADCELL_VSSIO_H + FIXED ( 5690000 1932000 ) W ;
550-
- u_vzz_12 PADCELL_VSSIO_H + FIXED ( 5690000 2636000 ) W ;
551-
- u_vzz_13 PADCELL_VSSIO_H + FIXED ( 5690000 3164000 ) W ;
552-
- u_vzz_14 PADCELL_VSSIO_H + FIXED ( 5690000 3868000 ) W ;
553-
- u_vzz_15 PADCELL_VSSIO_H + FIXED ( 5690000 4396000 ) W ;
554-
- u_vzz_16 PADCELL_VSSIO_H + FIXED ( 5690000 4924000 ) W ;
548+
- u_vzz_10 PADCELL_VSSIO_H + FIXED ( 5690000 910000 ) W ;
549+
- u_vzz_11 PADCELL_VSSIO_H + FIXED ( 5690000 1210000 ) W ;
550+
- u_vzz_12 PADCELL_VSSIO_H + FIXED ( 5690000 1610000 ) W ;
551+
- u_vzz_13 PADCELL_VSSIO_H + FIXED ( 5690000 1910000 ) W ;
552+
- u_vzz_14 PADCELL_VSSIO_H + FIXED ( 5690000 2310000 ) W ;
553+
- u_vzz_15 PADCELL_VSSIO_H + FIXED ( 5690000 2610000 ) W ;
554+
- u_vzz_16 PADCELL_VSSIO_H + FIXED ( 5690000 2910000 ) W ;
555555
- u_vzz_17 PADCELL_VSSIO_V + FIXED ( 5340000 5690000 ) FS ;
556556
- u_vzz_18 PADCELL_VSSIO_V + FIXED ( 4456000 5690000 ) FS ;
557557
- u_vzz_19 PADCELL_VSSIO_V + FIXED ( 4140000 5690000 ) FS ;
@@ -575,7 +575,7 @@ COMPONENTS 543 ;
575575
- u_vzz_6 PADCELL_VSSIO_V + FIXED ( 4216000 30000 ) N ;
576576
- u_vzz_7 PADCELL_VSSIO_V + FIXED ( 4768000 30000 ) N ;
577577
- u_vzz_8 PADCELL_VSSIO_V + FIXED ( 5504000 30000 ) N ;
578-
- u_vzz_9 PADCELL_VSSIO_H + FIXED ( 5690000 876000 ) W ;
578+
- u_vzz_9 PADCELL_VSSIO_H + FIXED ( 5690000 610000 ) W ;
579579
END COMPONENTS
580580
PINS 135 ;
581581
- p_bsg_tag_clk_i + NET p_bsg_tag_clk_i + SPECIAL + DIRECTION INPUT + USE SIGNAL

‎src/pad/test/place_pads_bumps_strategy.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -212,7 +212,7 @@ assign_io_bump -net p_ddr_dq_9_io -terminal u_ddr_dq_9_io/PAD BUMP_1_4
212212
assign_io_bump -net p_ddr_dq_8_io -terminal u_ddr_dq_8_io/PAD BUMP_0_4
213213

214214
# Place pads
215-
place_pads -mode uniform -row IO_EAST u_ddr_dq_23_io u_ddr_dq_22_io u_ddr_dq_21_io \
215+
place_pads -mode linear -row IO_EAST u_ddr_dq_23_io u_ddr_dq_22_io u_ddr_dq_21_io \
216216
u_vdd_4 u_vss_4 u_ddr_dq_20_io u_vzz_9 u_v18_9 u_ddr_dq_19_io \
217217
u_ddr_dq_18_io u_ddr_dq_17_io u_ddr_dq_16_io u_vzz_10 u_v18_10 \
218218
u_ddr_dq_31_io u_ddr_dq_30_io u_ddr_dq_29_io u_ddr_dq_28_io u_vzz_11 \

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