tidy

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

test/orfs/ram_8x7/BUILD

@@ -92,7 +92,7 @@ filegroup(
 [sim_test(
     name = "ram_8x7_{stage}_sim_test".format(stage = stage),
     cc_srcs = ["ram_8x7_sim.cpp"],
-    verilog = [":ram_8x7_{stage}.v".format(stage = stage) if stage != "source" else ":ram_8x7.sv"],
     module_top = "ram_8x7",
+    verilog = [":ram_8x7_{stage}.v".format(stage = stage) if stage != "source" else ":ram_8x7.sv"],
     #tags = ["manual"],
 ) for stage in STAGES[1:]]

test/orfs/ram_8x7/sim.bzl

@@ -23,13 +23,13 @@ def sim_test(
     """
     verilog_library(
         name = "{name}_split".format(name = name),
-        srcs =                [
+        srcs = [
             "//test/orfs/mock-array:asap7_files",
-                #    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v",
-                #    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_INVBUF_RVT_TT_201020.v",
-                #    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
-                #    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/dff.v",
-               ] + verilog,
+            #    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v",
+            #    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_INVBUF_RVT_TT_201020.v",
+            #    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
+            #    "@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/dff.v",
+        ] + verilog,
         visibility = ["//visibility:public"],
         tags = ["manual"],
     )
@@ -46,17 +46,17 @@ def sim_test(
         trace = True,
         visibility = ["//visibility:public"],
         vopts = [
-                    "--timescale 1ps/1ps",
-                    "-Wall",
-                    "-Wno-DECLFILENAME",
-                    "-Wno-UNUSEDSIGNAL",
-                    "-Wno-PINMISSING",
-                    "--trace-underscore",
-                    # inline all PDK modules to speed up compilation
-                    "--flatten",
-                    # No-op option to retrigger a build
-                    # "-Wfuture-blah",
-                ],
+            "--timescale 1ps/1ps",
+            "-Wall",
+            "-Wno-DECLFILENAME",
+            "-Wno-UNUSEDSIGNAL",
+            "-Wno-PINMISSING",
+            "--trace-underscore",
+            # inline all PDK modules to speed up compilation
+            "--flatten",
+            # No-op option to retrigger a build
+            # "-Wfuture-blah",
+        ],
     )
 
     cc_test(