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eder-matheuseder-matheus
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Merge pull request #8134 from The-OpenROAD-Project-staging/est_via_res
est: add via resistance when connecting pins to tree
2 parents f77d977 + 6d352c5 commit 3eafde8

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46 files changed

+834
-736
lines changed

‎src/cts/test/array.ok‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ Total number of Buffers Inserted: 556.
115115
Total number of Clock Subnets: 556.
116116
Total number of Sinks: 2475.
117117
Cells used:
118-
BUF_X4: 567
118+
BUF_X4: 566
119119
Dummys used:
120120
BUF_X4: 2
121121
INV_X1: 1
@@ -125,16 +125,16 @@ Dummys used:
125125
[INFO RSZ-0048] Inserted 112 buffers in 38 nets.
126126
Placement Analysis
127127
---------------------------------
128-
total displacement 4576.2 u
128+
total displacement 4567.0 u
129129
average displacement 1.4 u
130130
max displacement 146.7 u
131-
original HPWL 189368.6 u
132-
legalized HPWL 190344.8 u
131+
original HPWL 189367.9 u
132+
legalized HPWL 190335.5 u
133133
delta HPWL 1 %
134134

135135
Clock clk
136136
1.08 source latency inst_5_7/clk ^
137-
-1.22 target latency inst_6_7/clk ^
137+
-1.21 target latency inst_6_7/clk ^
138138
0.00 CRPR
139139
--------------
140140
-0.14 setup skew
@@ -176,7 +176,7 @@ Path Type: max
176176
0.04 1.07 ^ wire11/Z (BUF_X8)
177177
0.04 1.11 ^ wire10/Z (BUF_X8)
178178
0.05 1.16 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
179-
0.00 1.17 ^ inst_1_1/clk (array_tile)
179+
0.00 1.16 ^ inst_1_1/clk (array_tile)
180180
0.21 1.38 ^ inst_1_1/e_out (array_tile)
181181
0.00 1.38 ^ inst_2_1/w_in (array_tile)
182182
1.38 data arrival time

‎src/cts/test/array_ins_delay.ok‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ delta HPWL 1 %
124124

125125
Clock clk
126126
1.08 source latency inst_5_7/clk ^
127-
-1.22 target latency inst_6_7/clk ^
127+
-1.21 target latency inst_6_7/clk ^
128128
0.00 CRPR
129129
--------------
130130
-0.14 setup skew
@@ -166,7 +166,7 @@ Path Type: max
166166
0.04 1.07 ^ wire11/Z (BUF_X8)
167167
0.04 1.11 ^ wire10/Z (BUF_X8)
168168
0.05 1.16 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
169-
0.00 1.17 ^ inst_1_1/clk (array_tile)
169+
0.00 1.16 ^ inst_1_1/clk (array_tile)
170170
0.21 1.38 ^ inst_1_1/e_out (array_tile)
171171
0.00 1.38 ^ inst_2_1/w_in (array_tile)
172172
1.38 data arrival time

‎src/cts/test/array_no_blockages.ok‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,7 @@ delta HPWL 1 %
123123

124124
Clock clk
125125
1.05 source latency inst_5_4/clk ^
126-
-1.17 target latency inst_6_4/clk ^
126+
-1.16 target latency inst_6_4/clk ^
127127
0.00 CRPR
128128
--------------
129129
-0.12 setup skew

‎src/cts/test/array_repair_clock_nets.ok‎

Lines changed: 103 additions & 99 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ Total number of Sinks: 2475.
119119
Cells used:
120120
BUF_X16: 11
121121
BUF_X32: 5
122-
BUF_X4: 557
122+
BUF_X4: 558
123123
BUF_X8: 96
124124
Dummys used:
125125
BUF_X4: 2
@@ -128,16 +128,16 @@ Dummys used:
128128
[INFO RSZ-0058] Using max wire length 693um.
129129
Placement Analysis
130130
---------------------------------
131-
total displacement 4507.3 u
131+
total displacement 4508.1 u
132132
average displacement 1.4 u
133133
max displacement 146.7 u
134-
original HPWL 189360.8 u
135-
legalized HPWL 190290.2 u
134+
original HPWL 189361.4 u
135+
legalized HPWL 190291.0 u
136136
delta HPWL 0 %
137137

138138
Clock clk
139-
1.08 source latency inst_5_7/clk ^
140-
-1.22 target latency inst_6_7/clk ^
139+
1.09 source latency inst_5_7/clk ^
140+
-1.23 target latency inst_6_7/clk ^
141141
0.00 CRPR
142142
--------------
143143
-0.14 setup skew
@@ -160,29 +160,30 @@ Path Type: max
160160
0.06 0.30 ^ wire4/Z (BUF_X32)
161161
0.06 0.36 ^ wire3/Z (BUF_X32)
162162
0.04 0.39 ^ wire2/Z (BUF_X32)
163-
0.07 0.46 ^ clkbuf_0_clk/Z (BUF_X4)
164-
0.04 0.50 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
165-
0.04 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
166-
0.04 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
167-
0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
168-
0.04 0.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
169-
0.03 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
170-
0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
171-
0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
172-
0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
173-
0.04 0.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
174-
0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
175-
0.03 0.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
176-
0.03 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
177-
0.04 0.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
178-
0.05 1.02 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
179-
0.04 1.07 ^ wire11/Z (BUF_X8)
180-
0.04 1.11 ^ wire10/Z (BUF_X8)
181-
0.05 1.16 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
182-
0.00 1.17 ^ inst_1_1/clk (array_tile)
183-
0.21 1.38 ^ inst_1_1/e_out (array_tile)
184-
0.00 1.38 ^ inst_2_1/w_in (array_tile)
185-
1.38 data arrival time
163+
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
164+
0.04 0.48 ^ delaybuf_0_clk/Z (BUF_X4)
165+
0.04 0.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
166+
0.04 0.56 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
167+
0.04 0.60 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
168+
0.03 0.63 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
169+
0.04 0.67 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
170+
0.03 0.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
171+
0.03 0.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
172+
0.03 0.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
173+
0.03 0.81 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
174+
0.04 0.85 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
175+
0.03 0.88 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
176+
0.03 0.91 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
177+
0.03 0.95 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
178+
0.04 0.99 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
179+
0.05 1.04 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
180+
0.04 1.08 ^ wire11/Z (BUF_X8)
181+
0.04 1.13 ^ wire10/Z (BUF_X8)
182+
0.05 1.18 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
183+
0.00 1.18 ^ inst_1_1/clk (array_tile)
184+
0.21 1.39 ^ inst_1_1/e_out (array_tile)
185+
0.00 1.39 ^ inst_2_1/w_in (array_tile)
186+
1.39 data arrival time
186187

187188
5.00 5.00 clock clk (rise edge)
188189
0.00 5.00 clock source latency
@@ -195,31 +196,32 @@ Path Type: max
195196
0.06 5.30 ^ wire4/Z (BUF_X32)
196197
0.06 5.36 ^ wire3/Z (BUF_X32)
197198
0.04 5.39 ^ wire2/Z (BUF_X32)
198-
0.07 5.46 ^ clkbuf_0_clk/Z (BUF_X4)
199-
0.04 5.50 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
200-
0.04 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
201-
0.04 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
202-
0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
203-
0.04 5.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
204-
0.03 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
205-
0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
206-
0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
207-
0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
208-
0.04 5.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
209-
0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
210-
0.03 5.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
211-
0.03 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
212-
0.04 5.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
213-
0.05 6.02 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
214-
0.04 6.06 ^ max_length13/Z (BUF_X8)
215-
0.04 6.09 ^ wire12/Z (BUF_X8)
216-
0.02 6.12 ^ inst_2_1/clk (array_tile)
217-
0.00 6.12 clock reconvergence pessimism
218-
-0.05 6.07 library setup time
219-
6.07 data required time
199+
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
200+
0.04 5.48 ^ delaybuf_0_clk/Z (BUF_X4)
201+
0.04 5.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
202+
0.04 5.56 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
203+
0.04 5.60 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
204+
0.03 5.63 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
205+
0.04 5.67 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
206+
0.03 5.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
207+
0.03 5.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
208+
0.03 5.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
209+
0.03 5.81 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
210+
0.04 5.85 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
211+
0.03 5.88 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
212+
0.03 5.91 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
213+
0.03 5.95 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
214+
0.04 5.99 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
215+
0.05 6.04 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
216+
0.04 6.08 ^ max_length13/Z (BUF_X8)
217+
0.04 6.11 ^ wire12/Z (BUF_X8)
218+
0.02 6.13 ^ inst_2_1/clk (array_tile)
219+
0.00 6.13 clock reconvergence pessimism
220+
-0.05 6.08 library setup time
221+
6.08 data required time
220222
---------------------------------------------------------
221-
6.07 data required time
222-
-1.38 data arrival time
223+
6.08 data required time
224+
-1.39 data arrival time
223225
---------------------------------------------------------
224226
4.69 slack (MET)
225227

@@ -242,28 +244,29 @@ Path Type: max
242244
0.06 0.30 ^ wire4/Z (BUF_X32)
243245
0.06 0.36 ^ wire3/Z (BUF_X32)
244246
0.04 0.39 ^ wire2/Z (BUF_X32)
245-
0.07 0.46 ^ clkbuf_0_clk/Z (BUF_X4)
246-
0.04 0.50 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
247-
0.04 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
248-
0.04 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
249-
0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
250-
0.04 0.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
251-
0.03 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
252-
0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
253-
0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
254-
0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
255-
0.04 0.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
256-
0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
257-
0.03 0.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
258-
0.03 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
259-
0.04 0.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
260-
0.05 1.02 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
261-
0.04 1.06 ^ max_length13/Z (BUF_X8)
262-
0.04 1.09 ^ wire12/Z (BUF_X8)
263-
0.02 1.12 ^ inst_2_1/clk (array_tile)
264-
0.21 1.33 ^ inst_2_1/e_out (array_tile)
265-
0.00 1.33 ^ inst_3_1/w_in (array_tile)
266-
1.33 data arrival time
247+
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
248+
0.04 0.48 ^ delaybuf_0_clk/Z (BUF_X4)
249+
0.04 0.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
250+
0.04 0.56 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
251+
0.04 0.60 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
252+
0.03 0.63 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
253+
0.04 0.67 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
254+
0.03 0.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
255+
0.03 0.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
256+
0.03 0.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
257+
0.03 0.81 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
258+
0.04 0.85 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
259+
0.03 0.88 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
260+
0.03 0.91 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
261+
0.03 0.95 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
262+
0.04 0.99 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
263+
0.05 1.04 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
264+
0.04 1.08 ^ max_length13/Z (BUF_X8)
265+
0.04 1.11 ^ wire12/Z (BUF_X8)
266+
0.02 1.13 ^ inst_2_1/clk (array_tile)
267+
0.21 1.35 ^ inst_2_1/e_out (array_tile)
268+
0.00 1.35 ^ inst_3_1/w_in (array_tile)
269+
1.35 data arrival time
267270

268271
5.00 5.00 clock clk (rise edge)
269272
0.00 5.00 clock source latency
@@ -276,31 +279,32 @@ Path Type: max
276279
0.06 5.30 ^ wire4/Z (BUF_X32)
277280
0.06 5.36 ^ wire3/Z (BUF_X32)
278281
0.04 5.39 ^ wire2/Z (BUF_X32)
279-
0.07 5.46 ^ clkbuf_0_clk/Z (BUF_X4)
280-
0.04 5.50 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
281-
0.04 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
282-
0.04 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
283-
0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
284-
0.04 5.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
285-
0.03 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
286-
0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
287-
0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
288-
0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
289-
0.04 5.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
290-
0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
291-
0.03 5.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
292-
0.03 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
293-
0.04 5.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
294-
0.05 6.02 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
295-
0.04 6.06 ^ max_length13/Z (BUF_X8)
296-
0.05 6.11 ^ clkbuf_leaf_118_clk/Z (BUF_X4)
297-
0.00 6.11 ^ inst_3_1/clk (array_tile)
298-
0.00 6.11 clock reconvergence pessimism
299-
-0.05 6.06 library setup time
300-
6.06 data required time
282+
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
283+
0.04 5.48 ^ delaybuf_0_clk/Z (BUF_X4)
284+
0.04 5.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
285+
0.04 5.56 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
286+
0.04 5.60 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
287+
0.03 5.63 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
288+
0.04 5.67 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
289+
0.03 5.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
290+
0.03 5.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
291+
0.03 5.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
292+
0.03 5.81 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
293+
0.04 5.85 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
294+
0.03 5.88 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
295+
0.03 5.91 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
296+
0.03 5.95 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
297+
0.04 5.99 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
298+
0.05 6.04 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
299+
0.04 6.08 ^ max_length13/Z (BUF_X8)
300+
0.05 6.13 ^ clkbuf_leaf_118_clk/Z (BUF_X4)
301+
0.00 6.13 ^ inst_3_1/clk (array_tile)
302+
0.00 6.13 clock reconvergence pessimism
303+
-0.05 6.08 library setup time
304+
6.08 data required time
301305
---------------------------------------------------------
302-
6.06 data required time
303-
-1.33 data arrival time
306+
6.08 data required time
307+
-1.35 data arrival time
304308
---------------------------------------------------------
305309
4.73 slack (MET)
306310

‎src/est/include/est/EstimateParasitics.h‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,9 @@ class EstimateParasitics : public dbStaState
131131
// Return values.
132132
double& res,
133133
double& cap) const;
134+
void addClkLayer(odb::dbTechLayer* layer);
135+
void addSignalLayer(odb::dbTechLayer* layer);
136+
void sortClkAndSignalLayers();
134137
// Set the resistance and capacitance used for horizontal parasitics on signal
135138
// nets.
136139
void setHWireSignalRC(const Corner* corner,
@@ -251,11 +254,16 @@ class EstimateParasitics : public dbStaState
251254
float subtreeLoad(SteinerTree* tree,
252255
float cap_per_micron,
253256
SteinerPt pt) const;
257+
odb::dbTechLayer* getPinLayer(const Pin* pin);
258+
double computeAverageCutResistance(Corner* corner);
254259
void parasiticNodeConnectPins(Parasitic* parasitic,
255260
ParasiticNode* node,
256261
SteinerTree* tree,
257262
SteinerPt pt,
258-
size_t& resistor_id);
263+
size_t& resistor_id,
264+
Corner* corner,
265+
std::set<const Pin*>& connected_pins,
266+
bool is_clk);
259267
void net2Pins(const Net* net, const Pin*& pin1, const Pin*& pin2) const;
260268
double dbuToMeters(int dist) const;
261269

@@ -269,6 +277,8 @@ class EstimateParasitics : public dbStaState
269277
dbBlock* block_ = nullptr;
270278
std::unique_ptr<OdbCallBack> db_cbk_;
271279

280+
std::vector<odb::dbTechLayer*> signal_layers_;
281+
std::vector<odb::dbTechLayer*> clk_layers_;
272282
// Layer RC per wire length indexed by layer->getNumber(), corner->index
273283
std::vector<std::vector<double>> layer_res_; // ohms/meter
274284
std::vector<std::vector<double>> layer_cap_; // Farads/meter

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