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arthurjoloarthurjolo
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update delay buffer insertion CTS messages
Signed-off-by: arthurjolo <[email protected]>
1 parent eb67b17 commit 3fc3a23

17 files changed

+59
-16
lines changed

‎src/cts/src/LatencyBalancer.cpp‎

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,13 @@ namespace cts {
2626

2727
using utl::CTS;
2828

29-
void LatencyBalancer::run()
29+
int LatencyBalancer::run()
3030
{
31+
logger_->info(
32+
CTS,
33+
33,
34+
"Balancing latancy for clock {}",
35+
root_->getClock().getSdcName());
3136
worseDelay_ = std::numeric_limits<float>::min();
3237
delayBufIndex_ = 0;
3338
initSta();
@@ -36,15 +41,15 @@ void LatencyBalancer::run()
3641
odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str());
3742
sta::Cell* masterCell = network_->dbToSta(master);
3843
sta::LibertyCell* libertyCell = network_->libertyCell(masterCell);
39-
buffer_delay_ = computeBufferDelay(libertyCell, 0);
44+
bufferDelay_ = computeBufferDelay(libertyCell, 0);
4045
balanceLatencies(0);
41-
debugPrint(logger_,
46+
logger_->info(
4247
CTS,
43-
"insertion delay",
44-
1,
45-
"inserted {} delay buffers for clock: {}",
48+
36,
49+
" inserted {} delay buffers",
4650
delayBufIndex_,
4751
root_->getClock().getSdcName());
52+
return delayBufIndex_;
4853
}
4954

5055
void LatencyBalancer::initSta()
@@ -336,8 +341,8 @@ void LatencyBalancer::balanceLatencies(int nodeId)
336341
3,
337342
"For node {}, isert {:2f} buffers",
338343
node->name,
339-
(worseDelay_ - node->delay) / buffer_delay_);
340-
node->nBuffInsert = (int) ((worseDelay_ - node->delay) / buffer_delay_);
344+
(worseDelay_ - node->delay) / bufferDelay_);
345+
node->nBuffInsert = (int) ((worseDelay_ - node->delay) / bufferDelay_);
341346
}
342347
return;
343348
}

‎src/cts/src/LatencyBalancer.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ class LatencyBalancer
6767
{
6868
}
6969

70-
void run();
70+
int run();
7171

7272
private:
7373
void initSta();
@@ -113,7 +113,7 @@ class LatencyBalancer
113113
sta::Graph* timingGraph_ = nullptr;
114114
double wireSegmentUnit_;
115115
float worseDelay_;
116-
float buffer_delay_;
116+
float bufferDelay_;
117117
int delayBufIndex_;
118118
std::vector<GraphNode> graph_;
119119
std::map<std::string, TreeBuilder*> inst2builder_;

‎src/cts/src/TritonCTS.cpp‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2315,6 +2315,7 @@ void TritonCTS::balanceMacroRegisterLatencies()
23152315

23162316
// Visit builders from bottom up such that latencies are adjusted near bottom
23172317
// trees first
2318+
int totalDelayBuff = 0;
23182319
est::IncrementalParasiticsGuard parasitics_guard(estimate_parasitics_);
23192320
for (auto iter = builders_.rbegin(); iter != builders_.rend(); ++iter) {
23202321
TreeBuilder* builder = iter->get();
@@ -2327,10 +2328,13 @@ void TritonCTS::balanceMacroRegisterLatencies()
23272328
network_,
23282329
openSta_,
23292330
techChar_->getLengthUnit());
2330-
balancer.run();
2331+
totalDelayBuff += balancer.run();
23312332
parasitics_guard.update();
23322333
}
23332334
}
2335+
if(totalDelayBuff) {
2336+
logger_->info(CTS, 37, "Total number of delay buffers: {}", totalDelayBuff);
2337+
}
23342338
}
23352339

23362340
float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex,

‎src/cts/test/array.ok‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,9 @@
110110
[INFO CTS-0101] Average sink wire length 4121.94 um
111111
[INFO CTS-0102] Path depth 17 - 17
112112
[INFO CTS-0207] Leaf load cells 4
113+
[INFO CTS-0033] Balancing latancy for clock clk
114+
[INFO CTS-0036] inserted 10 delay buffers
115+
[INFO CTS-0037] Total number of delay buffers: 10
113116
Total number of Clock Roots: 2.
114117
Total number of Buffers Inserted: 556.
115118
Total number of Clock Subnets: 556.

‎src/cts/test/array_ins_delay.ok‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,9 @@
110110
[INFO CTS-0101] Average sink wire length 4121.94 um
111111
[INFO CTS-0102] Path depth 17 - 17
112112
[INFO CTS-0207] Leaf load cells 4
113+
[INFO CTS-0033] Balancing latancy for clock clk
114+
[INFO CTS-0036] inserted 10 delay buffers
115+
[INFO CTS-0037] Total number of delay buffers: 10
113116
[INFO RSZ-0058] Using max wire length 693um.
114117
[INFO RSZ-0047] Found 38 long wires.
115118
[INFO RSZ-0048] Inserted 111 buffers in 38 nets.

‎src/cts/test/array_no_blockages.ok‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,9 @@
109109
[INFO CTS-0101] Average sink wire length 4117.74 um
110110
[INFO CTS-0102] Path depth 17 - 17
111111
[INFO CTS-0207] Leaf load cells 4
112+
[INFO CTS-0033] Balancing latancy for clock clk
113+
[INFO CTS-0036] inserted 11 delay buffers
114+
[INFO CTS-0037] Total number of delay buffers: 11
112115
[INFO RSZ-0058] Using max wire length 693um.
113116
[INFO RSZ-0047] Found 38 long wires.
114117
[INFO RSZ-0048] Inserted 111 buffers in 38 nets.

‎src/cts/test/array_repair_clock_nets.ok‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,8 @@
112112
[INFO CTS-0207] Leaf load cells 4
113113
[INFO RSZ-0047] Found 38 long wires.
114114
[INFO RSZ-0048] Inserted 112 buffers in 38 nets.
115+
[INFO CTS-0033] Balancing latancy for clock clk
116+
[INFO CTS-0036] inserted 0 delay buffers
115117
Total number of Clock Roots: 2.
116118
Total number of Buffers Inserted: 556.
117119
Total number of Clock Subnets: 556.

‎src/cts/test/balance_levels.ok‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -126,4 +126,6 @@
126126
[INFO CTS-0101] Average sink wire length 65.88 um
127127
[INFO CTS-0102] Path depth 2 - 2
128128
[INFO CTS-0207] Leaf load cells 30
129+
[INFO CTS-0033] Balancing latancy for clock clk
130+
[INFO CTS-0036] inserted 0 delay buffers
129131
No differences found.

‎src/cts/test/gated_clock1.ok‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,8 @@
133133
[DEBUG CTS-insertion delay] top buffer delay for macro tree clkbuf_0_clk is 2.480e-11
134134
[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_regs_0_clk is 2.480e-11
135135
[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_0_gclk1 is 5.007e-11
136+
[INFO CTS-0033] Balancing latancy for clock clk
136137
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (101013 149105)
137138
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (102026 98350)
138-
[DEBUG CTS-insertion delay] inserted 2 delay buffers for clock: clk
139+
[INFO CTS-0036] inserted 2 delay buffers
140+
[INFO CTS-0037] Total number of delay buffers: 2

‎src/cts/test/gated_clock2.ok‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -234,6 +234,7 @@
234234
[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_regs_1_clk is 2.938e-11
235235
[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_0_gclk2 is 3.354e-11
236236
[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_0_gclk3 is 3.945e-11
237+
[INFO CTS-0033] Balancing latancy for clock clk
237238
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (53610 163461)
238239
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (53625 160743)
239240
[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_clk is inserted at (104465 160125)
@@ -243,4 +244,5 @@
243244
[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_clk is inserted at (101216 138954)
244245
[DEBUG CTS-insertion delay] new delay buffer delaybuf_7_clk is inserted at (101824 108501)
245246
[DEBUG CTS-insertion delay] new delay buffer delaybuf_8_clk is inserted at (102432 78048)
246-
[DEBUG CTS-insertion delay] inserted 9 delay buffers for clock: clk
247+
[INFO CTS-0036] inserted 9 delay buffers
248+
[INFO CTS-0037] Total number of delay buffers: 9

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