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arthurjoloarthurjolo
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update ok files
Signed-off-by: arthurjolo <[email protected]>
1 parent 6940ccb commit 40740ca

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6 files changed

+275
-243
lines changed

6 files changed

+275
-243
lines changed

‎src/cts/test/gated_clock1.ok‎

Lines changed: 142 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -8,130 +8,193 @@
88
[INFO CTS-0052] The following clock buffers will be used for CTS:
99
CLKBUF_X3
1010
[INFO CTS-0049] Characterization buffer is CLKBUF_X3.
11+
[DEBUG CTS-clock gate cloning] Threshold = 40000
12+
[DEBUG CTS-clock gate cloning] Found 4 clusters
13+
[DEBUG CTS-clock gate cloning] Creating clone clone_1_gclk1 from gclk1
14+
[DEBUG CTS-clock gate cloning] New clone net clonenet_1_gclk1
15+
[DEBUG CTS-clock gate cloning] Connects sink ff279/CK
16+
[DEBUG CTS-clock gate cloning] Connects sink ff280/CK
17+
[DEBUG CTS-clock gate cloning] Connects sink ff281/CK
18+
[DEBUG CTS-clock gate cloning] Connects sink ff282/CK
19+
[DEBUG CTS-clock gate cloning] Connects sink ff283/CK
20+
[DEBUG CTS-clock gate cloning] Connects sink ff284/CK
21+
[DEBUG CTS-clock gate cloning] Connects sink ff285/CK
22+
[DEBUG CTS-clock gate cloning] Connects sink ff286/CK
23+
[DEBUG CTS-clock gate cloning] Connects sink ff287/CK
24+
[DEBUG CTS-clock gate cloning] Original cell gclk1
25+
[DEBUG CTS-clock gate cloning] Original net gclk1
26+
[DEBUG CTS-clock gate cloning] Connects sink ff14/CK
27+
[DEBUG CTS-clock gate cloning] Connects sink ff15/CK
28+
[DEBUG CTS-clock gate cloning] Connects sink ff16/CK
29+
[DEBUG CTS-clock gate cloning] Connects sink ff17/CK
30+
[DEBUG CTS-clock gate cloning] Creating clone clone_2_gclk1 from gclk1
31+
[DEBUG CTS-clock gate cloning] New clone net clonenet_2_gclk1
32+
[DEBUG CTS-clock gate cloning] Connects sink ff0/CK
33+
[DEBUG CTS-clock gate cloning] Connects sink ff1/CK
34+
[DEBUG CTS-clock gate cloning] Created 2 clones
1135
[INFO CTS-0007] Net "clk" found for clock "clk".
12-
[INFO CTS-0011] Clock net "clk" for macros has 1 sinks.
13-
[INFO CTS-0011] Clock net "clk_regs" for registers has 144 sinks.
14-
[INFO CTS-0010] Clock net "gclk1" has 144 sinks.
15-
[INFO CTS-0008] TritonCTS found 3 clock nets.
36+
[INFO CTS-0011] Clock net "clk" for macros has 3 sinks.
37+
[INFO CTS-0011] Clock net "clk_regs" for registers has 273 sinks.
38+
[INFO CTS-0010] Clock net "clonenet_2_gclk1" has 2 sinks.
39+
[INFO CTS-0010] Clock net "clonenet_1_gclk1" has 9 sinks.
40+
[INFO CTS-0010] Clock net "gclk1" has 4 sinks.
41+
[INFO CTS-0008] TritonCTS found 5 clock nets.
1642
[INFO CTS-0097] Characterization used 1 buffer(s) types.
1743
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
1844
[INFO CTS-0027] Generating H-Tree topology for net clk.
19-
[INFO CTS-0028] Total number of sinks: 1.
45+
[INFO CTS-0028] Total number of sinks: 3.
2046
[INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 50.0 um.
2147
[INFO CTS-0030] Number of static layers: 1.
2248
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
2349
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
24-
[INFO CTS-0023] Original sink region: [(53595, 166180), (53595, 166180)].
25-
[INFO CTS-0024] Normalized sink region: [(3.82821, 11.87), (3.82821, 11.87)].
26-
[INFO CTS-0025] Width: 0.0000.
27-
[INFO CTS-0026] Height: 0.0000.
50+
[INFO CTS-0023] Original sink region: [(17875, 8150), (183935, 173010)].
51+
[INFO CTS-0024] Normalized sink region: [(1.27679, 0.582143), (13.1382, 12.3579)].
52+
[INFO CTS-0025] Width: 11.8614.
53+
[INFO CTS-0026] Height: 11.7757.
2854
Level 1
29-
Direction: Vertical
30-
Sinks per sub-region: 1
31-
Sub-region size: 0.0000 X 0.0000
32-
[INFO CTS-0034] Segment length (rounded): 1.
55+
Direction: Horizontal
56+
Sinks per sub-region: 2
57+
Sub-region size: 5.9307 X 11.7757
58+
[INFO CTS-0034] Segment length (rounded): 2.
3359
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
34-
[INFO CTS-0035] Number of sinks covered: 1.
60+
[INFO CTS-0035] Number of sinks covered: 3.
3561
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
3662
[INFO CTS-0027] Generating H-Tree topology for net clk_regs.
37-
[INFO CTS-0028] Total number of sinks: 144.
63+
[INFO CTS-0028] Total number of sinks: 273.
3864
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
3965
[INFO CTS-0030] Number of static layers: 1.
4066
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
4167
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
42-
[INFO CTS-0023] Original sink region: [(8930, 7170), (196650, 85570)].
43-
[INFO CTS-0024] Normalized sink region: [(0.637857, 0.512143), (14.0464, 6.11214)].
44-
[INFO CTS-0025] Width: 13.4086.
45-
[INFO CTS-0026] Height: 5.6000.
68+
[INFO CTS-0206] Best clustering solution was found from clustering size of 10 and clustering diameter of 50.
69+
[INFO CTS-0019] Total number of sinks after clustering: 38.
70+
[INFO CTS-0024] Normalized sink region: [(1.425, 0.912143), (13.2981, 11.6662)].
71+
[INFO CTS-0025] Width: 11.8731.
72+
[INFO CTS-0026] Height: 10.7541.
4673
Level 1
4774
Direction: Horizontal
48-
Sinks per sub-region: 72
49-
Sub-region size: 6.7043 X 5.6000
50-
[INFO CTS-0034] Segment length (rounded): 4.
75+
Sinks per sub-region: 19
76+
Sub-region size: 5.9365 X 10.7541
77+
[INFO CTS-0034] Segment length (rounded): 2.
5178
Level 2
5279
Direction: Vertical
53-
Sinks per sub-region: 36
54-
Sub-region size: 6.7043 X 2.8000
55-
[INFO CTS-0034] Segment length (rounded): 1.
56-
Level 3
80+
Sinks per sub-region: 10
81+
Sub-region size: 5.9365 X 5.3770
82+
[INFO CTS-0034] Segment length (rounded): 2.
83+
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
84+
[INFO CTS-0035] Number of sinks covered: 38.
85+
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
86+
[INFO CTS-0027] Generating H-Tree topology for net clonenet_2_gclk1.
87+
[INFO CTS-0028] Total number of sinks: 2.
88+
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
89+
[INFO CTS-0030] Number of static layers: 1.
90+
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
91+
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
92+
[INFO CTS-0023] Original sink region: [(8930, 7170), (19950, 7170)].
93+
[INFO CTS-0024] Normalized sink region: [(0.637857, 0.512143), (1.425, 0.512143)].
94+
[INFO CTS-0025] Width: 0.7871.
95+
[INFO CTS-0026] Height: 0.0000.
96+
Level 1
5797
Direction: Horizontal
58-
Sinks per sub-region: 18
59-
Sub-region size: 3.3521 X 2.8000
60-
[INFO CTS-0034] Segment length (rounded): 1.
61-
Level 4
62-
Direction: Vertical
63-
Sinks per sub-region: 9
64-
Sub-region size: 3.3521 X 1.4000
98+
Sinks per sub-region: 1
99+
Sub-region size: 0.3936 X 0.0000
65100
[INFO CTS-0034] Segment length (rounded): 1.
66101
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
67-
[INFO CTS-0035] Number of sinks covered: 144.
102+
[INFO CTS-0035] Number of sinks covered: 2.
68103
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
69-
[INFO CTS-0027] Generating H-Tree topology for net gclk1.
70-
[INFO CTS-0028] Total number of sinks: 144.
104+
[INFO CTS-0027] Generating H-Tree topology for net clonenet_1_gclk1.
105+
[INFO CTS-0028] Total number of sinks: 9.
71106
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
72107
[INFO CTS-0030] Number of static layers: 1.
73108
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
74109
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
75-
[INFO CTS-0023] Original sink region: [(8930, 96770), (196650, 172030)].
76-
[INFO CTS-0024] Normalized sink region: [(0.637857, 6.91214), (14.0464, 12.2879)].
77-
[INFO CTS-0025] Width: 13.4086.
78-
[INFO CTS-0026] Height: 5.3757.
110+
[INFO CTS-0023] Original sink region: [(108870, 172030), (196650, 172030)].
111+
[INFO CTS-0024] Normalized sink region: [(7.77643, 12.2879), (14.0464, 12.2879)].
112+
[INFO CTS-0025] Width: 6.2700.
113+
[INFO CTS-0026] Height: 0.0000.
79114
Level 1
80115
Direction: Horizontal
81-
Sinks per sub-region: 72
82-
Sub-region size: 6.7043 X 5.3757
83-
[INFO CTS-0034] Segment length (rounded): 4.
84-
Level 2
85-
Direction: Vertical
86-
Sinks per sub-region: 36
87-
Sub-region size: 6.7043 X 2.6879
116+
Sinks per sub-region: 5
117+
Sub-region size: 3.1350 X 0.0000
88118
[INFO CTS-0034] Segment length (rounded): 1.
89-
Level 3
119+
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
120+
[INFO CTS-0035] Number of sinks covered: 9.
121+
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
122+
[INFO CTS-0027] Generating H-Tree topology for net gclk1.
123+
[INFO CTS-0028] Total number of sinks: 4.
124+
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
125+
[INFO CTS-0030] Number of static layers: 1.
126+
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
127+
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
128+
[INFO CTS-0023] Original sink region: [(164350, 7170), (196650, 7170)].
129+
[INFO CTS-0024] Normalized sink region: [(11.7393, 0.512143), (14.0464, 0.512143)].
130+
[INFO CTS-0025] Width: 2.3071.
131+
[INFO CTS-0026] Height: 0.0000.
132+
Level 1
90133
Direction: Horizontal
91-
Sinks per sub-region: 18
92-
Sub-region size: 3.3521 X 2.6879
93-
[INFO CTS-0034] Segment length (rounded): 1.
94-
Level 4
95-
Direction: Vertical
96-
Sinks per sub-region: 9
97-
Sub-region size: 3.3521 X 1.3439
134+
Sinks per sub-region: 2
135+
Sub-region size: 1.1536 X 0.0000
98136
[INFO CTS-0034] Segment length (rounded): 1.
99137
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
100-
[INFO CTS-0035] Number of sinks covered: 144.
101-
[INFO CTS-0018] Created 2 clock buffers.
138+
[INFO CTS-0035] Number of sinks covered: 4.
139+
[INFO CTS-0018] Created 3 clock buffers.
102140
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
103141
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
104-
[INFO CTS-0015] Created 2 clock nets.
105-
[INFO CTS-0016] Fanout distribution for the current clock = 1:1..
142+
[INFO CTS-0015] Created 3 clock nets.
143+
[INFO CTS-0016] Fanout distribution for the current clock = 1:1, 2:1..
106144
[INFO CTS-0017] Max level of the clock tree: 1.
107-
[INFO CTS-0018] Created 17 clock buffers.
145+
[INFO CTS-0018] Created 43 clock buffers.
146+
[INFO CTS-0012] Minimum number of buffers in the clock path: 3.
147+
[INFO CTS-0013] Maximum number of buffers in the clock path: 3.
148+
[INFO CTS-0015] Created 43 clock nets.
149+
[INFO CTS-0016] Fanout distribution for the current clock = 6:1, 7:29, 8:9, 10:3..
150+
[INFO CTS-0017] Max level of the clock tree: 2.
151+
[INFO CTS-0018] Created 3 clock buffers.
108152
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
109153
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
110-
[INFO CTS-0015] Created 17 clock nets.
111-
[INFO CTS-0016] Fanout distribution for the current clock = 6:1, 7:3, 8:2, 9:4, 10:2, 11:3, 12:1..
112-
[INFO CTS-0017] Max level of the clock tree: 4.
113-
[INFO CTS-0018] Created 17 clock buffers.
154+
[INFO CTS-0015] Created 3 clock nets.
155+
[INFO CTS-0016] Fanout distribution for the current clock = 1:2..
156+
[INFO CTS-0017] Max level of the clock tree: 1.
157+
[INFO CTS-0018] Created 3 clock buffers.
158+
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
159+
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
160+
[INFO CTS-0015] Created 3 clock nets.
161+
[INFO CTS-0016] Fanout distribution for the current clock = 4:1, 5:1..
162+
[INFO CTS-0017] Max level of the clock tree: 1.
163+
[INFO CTS-0018] Created 3 clock buffers.
114164
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
115165
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
116-
[INFO CTS-0015] Created 17 clock nets.
117-
[INFO CTS-0016] Fanout distribution for the current clock = 7:3, 8:3, 9:6, 10:1, 11:1, 12:2..
118-
[INFO CTS-0017] Max level of the clock tree: 4.
119-
[INFO CTS-0124] Clock net "clk"
120-
[INFO CTS-0125] Sinks 1
166+
[INFO CTS-0015] Created 3 clock nets.
167+
[INFO CTS-0016] Fanout distribution for the current clock = 2:2..
168+
[INFO CTS-0017] Max level of the clock tree: 1.
169+
[INFO CTS-0098] Clock net "clk"
170+
[INFO CTS-0099] Sinks 3
171+
[INFO CTS-0100] Leaf buffers 0
172+
[INFO CTS-0101] Average sink wire length 142.21 um
173+
[INFO CTS-0102] Path depth 2 - 2
174+
[INFO CTS-0207] Leaf load cells 33
121175
[INFO CTS-0098] Clock net "clk_regs"
122-
[INFO CTS-0099] Sinks 159
176+
[INFO CTS-0099] Sinks 304
177+
[INFO CTS-0100] Leaf buffers 38
178+
[INFO CTS-0101] Average sink wire length 62.58 um
179+
[INFO CTS-0102] Path depth 2 - 3
180+
[INFO CTS-0207] Leaf load cells 33
181+
[INFO CTS-0098] Clock net "clonenet_2_gclk1"
182+
[INFO CTS-0099] Sinks 2
183+
[INFO CTS-0100] Leaf buffers 0
184+
[INFO CTS-0101] Average sink wire length 14.12 um
185+
[INFO CTS-0102] Path depth 2 - 2
186+
[INFO CTS-0207] Leaf load cells 33
187+
[INFO CTS-0098] Clock net "clonenet_1_gclk1"
188+
[INFO CTS-0099] Sinks 10
123189
[INFO CTS-0100] Leaf buffers 0
124-
[INFO CTS-0101] Average sink wire length 45.22 um
190+
[INFO CTS-0101] Average sink wire length 16.62 um
125191
[INFO CTS-0102] Path depth 2 - 2
126-
[INFO CTS-0207] Leaf load cells 29
192+
[INFO CTS-0207] Leaf load cells 33
127193
[INFO CTS-0098] Clock net "gclk1"
128-
[INFO CTS-0099] Sinks 158
194+
[INFO CTS-0099] Sinks 4
129195
[INFO CTS-0100] Leaf buffers 0
130-
[INFO CTS-0101] Average sink wire length 83.63 um
196+
[INFO CTS-0101] Average sink wire length 12.53 um
131197
[INFO CTS-0102] Path depth 2 - 2
132-
[INFO CTS-0207] Leaf load cells 29
198+
[INFO CTS-0207] Leaf load cells 33
133199
[INFO CTS-0033] Balancing latency for clock clk
134-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (101013 149105)
135-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (102026 98350)
136-
[INFO CTS-0036] inserted 2 delay buffers
137-
[INFO CTS-0037] Total number of delay buffers: 2
200+
[INFO CTS-0036] inserted 0 delay buffers

‎src/cts/test/gated_clock2.ok‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -24,15 +24,15 @@
2424
[INFO CTS-0030] Number of static layers: 1.
2525
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
2626
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
27-
[INFO CTS-0023] Original sink region: [(53595, 151620), (147835, 166180)].
28-
[INFO CTS-0024] Normalized sink region: [(3.82821, 10.83), (10.5596, 11.87)].
29-
[INFO CTS-0025] Width: 6.7314.
30-
[INFO CTS-0026] Height: 1.0400.
27+
[INFO CTS-0023] Original sink region: [(56825, 136220), (156195, 144690)].
28+
[INFO CTS-0024] Normalized sink region: [(4.05893, 9.73), (11.1568, 10.335)].
29+
[INFO CTS-0025] Width: 7.0979.
30+
[INFO CTS-0026] Height: 0.6050.
3131
Level 1
3232
Direction: Horizontal
3333
Sinks per sub-region: 1
34-
Sub-region size: 3.3657 X 1.0400
35-
[INFO CTS-0034] Segment length (rounded): 1.
34+
Sub-region size: 3.5489 X 0.6050
35+
[INFO CTS-0034] Segment length (rounded): 2.
3636
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
3737
[INFO CTS-0035] Number of sinks covered: 2.
3838
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
@@ -75,8 +75,8 @@
7575
[INFO CTS-0030] Number of static layers: 1.
7676
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
7777
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
78-
[INFO CTS-0023] Original sink region: [(53595, 102620), (53595, 102620)].
79-
[INFO CTS-0024] Normalized sink region: [(3.82821, 7.33), (3.82821, 7.33)].
78+
[INFO CTS-0023] Original sink region: [(56825, 115390), (56825, 115390)].
79+
[INFO CTS-0024] Normalized sink region: [(4.05893, 8.24214), (4.05893, 8.24214)].
8080
[INFO CTS-0025] Width: 0.0000.
8181
[INFO CTS-0026] Height: 0.0000.
8282
Level 1
@@ -199,7 +199,7 @@
199199
[INFO CTS-0098] Clock net "clk"
200200
[INFO CTS-0099] Sinks 2
201201
[INFO CTS-0100] Leaf buffers 0
202-
[INFO CTS-0101] Average sink wire length 47.55 um
202+
[INFO CTS-0101] Average sink wire length 59.43 um
203203
[INFO CTS-0102] Path depth 2 - 2
204204
[INFO CTS-0207] Leaf load cells 27
205205
[INFO CTS-0098] Clock net "clk_regs"
@@ -219,21 +219,21 @@
219219
[INFO CTS-0098] Clock net "gclk2"
220220
[INFO CTS-0099] Sinks 39
221221
[INFO CTS-0100] Leaf buffers 0
222-
[INFO CTS-0101] Average sink wire length 29.38 um
222+
[INFO CTS-0101] Average sink wire length 24.92 um
223223
[INFO CTS-0102] Path depth 2 - 2
224224
[INFO CTS-0207] Leaf load cells 27
225225
[INFO CTS-0098] Clock net "gclk3"
226226
[INFO CTS-0099] Sinks 78
227227
[INFO CTS-0100] Leaf buffers 0
228-
[INFO CTS-0101] Average sink wire length 37.31 um
228+
[INFO CTS-0101] Average sink wire length 29.90 um
229229
[INFO CTS-0102] Path depth 2 - 2
230230
[INFO CTS-0207] Leaf load cells 27
231231
[INFO CTS-0033] Balancing latency for clock clk
232-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (53610 163461)
233-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (53625 160743)
234-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_clk is inserted at (104465 160125)
235-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_clk is inserted at (107965 160125)
236-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_clk is inserted at (111465 160125)
232+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (55763 149135)
233+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (54701 153580)
234+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_clk is inserted at (113760 141680)
235+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_clk is inserted at (120760 141680)
236+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_clk is inserted at (127760 141680)
237237
[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_clk is inserted at (100608 169407)
238238
[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_clk is inserted at (101216 138954)
239239
[DEBUG CTS-insertion delay] new delay buffer delaybuf_7_clk is inserted at (101824 108501)

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