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Merge pull request #8693 from gudeh/gpl-new-regions
gpl: introduce region hard constraint
2 parents 8b193f4 + 92842dc commit 4534556

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‎src/cts/test/gated_clock4.ok‎

Lines changed: 51 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ Using 2 tracks default min distance between IO pins.
1414
[INFO GPL-0002] DBU: 2000
1515
[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um
1616
[INFO GPL-0004] CoreBBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
17+
[INFO GPL-0032] Initializing region: Top-level
1718
[INFO GPL-0006] Number of instances: 283
1819
[INFO GPL-0007] Movable instances: 283
1920
[INFO GPL-0008] Fixed instances: 0
@@ -23,24 +24,26 @@ Using 2 tracks default min distance between IO pins.
2324
[INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 1000.000 1000.000 ) um
2425
[INFO GPL-0013] Core BBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
2526
[INFO GPL-0016] Core area: 999570.012 um^2
27+
[INFO GPL-0014] Region name: top-level.
28+
[INFO GPL-0015] Region area: 999570.012 um^2
2629
[INFO GPL-0017] Fixed instances area: 0.000 um^2
2730
[INFO GPL-0018] Movable instances area: 1274.406 um^2
2831
[INFO GPL-0019] Utilization: 0.127 %
2932
[INFO GPL-0020] Standard cells area: 1274.406 um^2
3033
[INFO GPL-0021] Large instances area: 0.000 um^2
3134
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000010 HPWL: 3046720
3235
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000009 HPWL: 74872
33-
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000008 HPWL: 61933
34-
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000011 HPWL: 61930
35-
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000011 HPWL: 61914
36+
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000008 HPWL: 61495
37+
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000011 HPWL: 61497
38+
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000011 HPWL: 61495
3639
Placement Analysis
3740
---------------------------------
38-
total displacement 6901.7 u
39-
average displacement 24.4 u
40-
max displacement 36.1 u
41-
original HPWL 0.0 u
42-
legalized HPWL 399.2 u
43-
delta HPWL 2575271 %
41+
total displacement 6730.6 u
42+
average displacement 23.8 u
43+
max displacement 35.5 u
44+
original HPWL 0.8 u
45+
legalized HPWL 388.7 u
46+
delta HPWL 49070 %
4447

4548
[INFO CTS-0050] Root buffer is CLKBUF_X3.
4649
[INFO CTS-0051] Sink buffer is CLKBUF_X3.
@@ -115,19 +118,19 @@ delta HPWL 2575271 %
115118
[INFO CTS-0030] Number of static layers: 1.
116119
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
117120
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
118-
[INFO CTS-0023] Original sink region: [(951330, 1941970), (1054690, 1997970)].
119-
[INFO CTS-0024] Normalized sink region: [(67.9521, 138.712), (75.335, 142.712)].
120-
[INFO CTS-0025] Width: 7.3829.
121-
[INFO CTS-0026] Height: 4.0000.
121+
[INFO CTS-0023] Original sink region: [(964250, 1955630), (1041770, 1997970)].
122+
[INFO CTS-0024] Normalized sink region: [(68.875, 139.688), (74.4121, 142.712)].
123+
[INFO CTS-0025] Width: 5.5371.
124+
[INFO CTS-0026] Height: 3.0243.
122125
Level 1
123126
Direction: Horizontal
124127
Sinks per sub-region: 18
125-
Sub-region size: 3.6914 X 4.0000
126-
[INFO CTS-0034] Segment length (rounded): 2.
128+
Sub-region size: 2.7686 X 3.0243
129+
[INFO CTS-0034] Segment length (rounded): 1.
127130
Level 2
128131
Direction: Vertical
129132
Sinks per sub-region: 9
130-
Sub-region size: 3.6914 X 2.0000
133+
Sub-region size: 2.7686 X 1.5121
131134
[INFO CTS-0034] Segment length (rounded): 1.
132135
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
133136
[INFO CTS-0035] Number of sinks covered: 36.
@@ -156,19 +159,19 @@ delta HPWL 2575271 %
156159
[INFO CTS-0030] Number of static layers: 1.
157160
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
158161
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
159-
[INFO CTS-0023] Original sink region: [(970710, 1964370), (1035310, 1997970)].
160-
[INFO CTS-0024] Normalized sink region: [(69.3364, 140.312), (73.9507, 142.712)].
161-
[INFO CTS-0025] Width: 4.6143.
162-
[INFO CTS-0026] Height: 2.4000.
162+
[INFO CTS-0023] Original sink region: [(957790, 1950030), (1048230, 1997970)].
163+
[INFO CTS-0024] Normalized sink region: [(68.4136, 139.288), (74.8736, 142.712)].
164+
[INFO CTS-0025] Width: 6.4600.
165+
[INFO CTS-0026] Height: 3.4243.
163166
Level 1
164167
Direction: Horizontal
165168
Sinks per sub-region: 18
166-
Sub-region size: 2.3071 X 2.4000
169+
Sub-region size: 3.2300 X 3.4243
167170
[INFO CTS-0034] Segment length (rounded): 1.
168171
Level 2
169172
Direction: Vertical
170173
Sinks per sub-region: 9
171-
Sub-region size: 2.3071 X 1.2000
174+
Sub-region size: 3.2300 X 1.7121
172175
[INFO CTS-0034] Segment length (rounded): 1.
173176
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
174177
[INFO CTS-0035] Number of sinks covered: 36.
@@ -202,19 +205,19 @@ delta HPWL 2575271 %
202205
[INFO CTS-0030] Number of static layers: 1.
203206
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
204207
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
205-
[INFO CTS-0023] Original sink region: [(964250, 1955630), (1041770, 1997970)].
206-
[INFO CTS-0024] Normalized sink region: [(68.875, 139.688), (74.4121, 142.712)].
207-
[INFO CTS-0025] Width: 5.5371.
208-
[INFO CTS-0026] Height: 3.0243.
208+
[INFO CTS-0023] Original sink region: [(970710, 1964370), (1035310, 1997970)].
209+
[INFO CTS-0024] Normalized sink region: [(69.3364, 140.312), (73.9507, 142.712)].
210+
[INFO CTS-0025] Width: 4.6143.
211+
[INFO CTS-0026] Height: 2.4000.
209212
Level 1
210213
Direction: Horizontal
211214
Sinks per sub-region: 18
212-
Sub-region size: 2.7686 X 3.0243
215+
Sub-region size: 2.3071 X 2.4000
213216
[INFO CTS-0034] Segment length (rounded): 1.
214217
Level 2
215218
Direction: Vertical
216219
Sinks per sub-region: 9
217-
Sub-region size: 2.7686 X 1.5121
220+
Sub-region size: 2.3071 X 1.2000
218221
[INFO CTS-0034] Segment length (rounded): 1.
219222
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
220223
[INFO CTS-0035] Number of sinks covered: 36.
@@ -228,13 +231,13 @@ delta HPWL 2575271 %
228231
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
229232
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
230233
[INFO CTS-0015] Created 17 clock nets.
231-
[INFO CTS-0016] Fanout distribution for the current clock = 5:1, 6:2, 7:4, 8:3, 9:2, 10:1, 12:2, 13:1..
234+
[INFO CTS-0016] Fanout distribution for the current clock = 4:1, 6:3, 7:3, 8:1, 9:4, 10:1, 11:1, 13:2..
232235
[INFO CTS-0017] Max level of the clock tree: 4.
233236
[INFO CTS-0018] Created 5 clock buffers.
234237
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
235238
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
236239
[INFO CTS-0015] Created 5 clock nets.
237-
[INFO CTS-0016] Fanout distribution for the current clock = 8:2, 10:2..
240+
[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 8:1, 9:1, 12:1..
238241
[INFO CTS-0017] Max level of the clock tree: 2.
239242
[INFO CTS-0018] Created 2 clock buffers.
240243
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
@@ -246,7 +249,7 @@ delta HPWL 2575271 %
246249
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
247250
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
248251
[INFO CTS-0015] Created 5 clock nets.
249-
[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 8:1, 9:1, 12:1..
252+
[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 8:1, 10:1, 11:1..
250253
[INFO CTS-0017] Max level of the clock tree: 2.
251254
[INFO CTS-0018] Created 5 clock buffers.
252255
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
@@ -267,45 +270,46 @@ delta HPWL 2575271 %
267270
[INFO CTS-0102] Path depth 2 - 2
268271
[INFO CTS-0207] Leaf load cells 26
269272
[INFO CTS-0098] Clock net "h1\/gclk5"
270-
[INFO CTS-0099] Sinks 149
273+
[INFO CTS-0099] Sinks 148
271274
[INFO CTS-0100] Leaf buffers 0
272-
[INFO CTS-0101] Average sink wire length 62.12 um
275+
[INFO CTS-0101] Average sink wire length 62.60 um
273276
[INFO CTS-0102] Path depth 2 - 2
274277
[INFO CTS-0207] Leaf load cells 26
275278
[INFO CTS-0098] Clock net "h1\/gclk2"
276-
[INFO CTS-0099] Sinks 38
279+
[INFO CTS-0099] Sinks 39
277280
[INFO CTS-0100] Leaf buffers 0
278-
[INFO CTS-0101] Average sink wire length 48.09 um
281+
[INFO CTS-0101] Average sink wire length 41.68 um
279282
[INFO CTS-0102] Path depth 2 - 2
280283
[INFO CTS-0207] Leaf load cells 26
281284
[INFO CTS-0124] Clock net "gclk4"
282285
[INFO CTS-0125] Sinks 1
283286
[INFO CTS-0098] Clock net "gclk4_regs"
284287
[INFO CTS-0099] Sinks 39
285288
[INFO CTS-0100] Leaf buffers 0
286-
[INFO CTS-0101] Average sink wire length 15.40 um
289+
[INFO CTS-0101] Average sink wire length 20.43 um
287290
[INFO CTS-0102] Path depth 2 - 2
288291
[INFO CTS-0207] Leaf load cells 26
289292
[INFO CTS-0098] Clock net "gclk3"
290293
[INFO CTS-0099] Sinks 39
291294
[INFO CTS-0100] Leaf buffers 0
292-
[INFO CTS-0101] Average sink wire length 40.51 um
295+
[INFO CTS-0101] Average sink wire length 40.27 um
293296
[INFO CTS-0102] Path depth 2 - 2
294297
[INFO CTS-0207] Leaf load cells 26
295298
[INFO CTS-0098] Clock net "gclk1"
296299
[INFO CTS-0099] Sinks 39
297300
[INFO CTS-0100] Leaf buffers 0
298-
[INFO CTS-0101] Average sink wire length 41.68 um
301+
[INFO CTS-0101] Average sink wire length 41.50 um
299302
[INFO CTS-0102] Path depth 2 - 2
300303
[INFO CTS-0207] Leaf load cells 26
301304
[INFO CTS-0033] Balancing latency for clock core
302-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_core is inserted at (969790 1979318)
303-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_core is inserted at (986525 1980856)
304-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_core is inserted at (949841 1972343)
305-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_core is inserted at (948218 1977861)
306-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_core is inserted at (968965 1966825)
307-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_core is inserted at (972465 1966825)
308-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_core is inserted at (975965 1966825)
309-
[INFO CTS-0036] inserted 7 delay buffers
310-
[INFO CTS-0037] Total number of delay buffers: 7
305+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_core is inserted at (973083 1973195)
306+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_core is inserted at (988171 1974209)
307+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_core is inserted at (980557 1962073)
308+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_core is inserted at (981650 1957322)
309+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_core is inserted at (982742 1952571)
310+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_core is inserted at (952260 1972302)
311+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_core is inserted at (960798 1966825)
312+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_7_core is inserted at (956131 1966825)
313+
[INFO CTS-0036] inserted 8 delay buffers
314+
[INFO CTS-0037] Total number of delay buffers: 8
311315
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