Merge pull request #8885 from braydenlouie/tapcell

ram: added tapcell placement and spacing

Author: maliberty

src/ram/include/ram/ram.h

@@ -46,7 +46,9 @@ class RamGen
                 int read_ports,
                 odb::dbMaster* storage_cell,
                 odb::dbMaster* tristate_cell,
-                odb::dbMaster* inv_cell);
+                odb::dbMaster* inv_cell,
+                odb::dbMaster* tapcell,
+                int max_tap_dist);
 
  private:
   void findMasters();
@@ -84,6 +86,8 @@ class RamGen
 
   odb::dbBTerm* makeBTerm(const std::string& name, odb::dbIoType io_type);
 
+  std::unique_ptr<Layout> generateTapColumn(int word_count, int tapcell_col);
+
   std::unique_ptr<Cell> makeDecoder(const std::string& prefix,
                                     int num_word,
                                     int read_ports,
@@ -104,6 +108,7 @@ class RamGen
   odb::dbMaster* and2_cell_{nullptr};
   odb::dbMaster* clock_gate_cell_{nullptr};
   odb::dbMaster* buffer_cell_{nullptr};
+  odb::dbMaster* tapcell_{nullptr};
 };
 
 }  // namespace ram

src/ram/src/layout.cpp

@@ -34,6 +34,8 @@ void Cell::addInst(dbInst* inst)
 
 void Cell::cellInit()
 {
+  width_ = 0;
+  height_ = 0;
   for (auto& inst : insts_) {
     Rect inst_box = inst->getBBox()->getBox();
     width_ += inst_box.dx();
@@ -166,6 +168,18 @@ void Grid::addLayout(std::unique_ptr<Layout> layout)
   layouts_.push_back(std::move(layout));
 }
 
+bool Grid::insertLayout(std::unique_ptr<Layout> layout, int index)
+{
+  if (index == layouts_.size()) {
+    layouts_.push_back(std::move(layout));
+  } else if (index < layouts_.size()) {
+    layouts_.insert(layouts_.begin() + index, std::move(layout));
+  } else if (index > layouts_.size()) {
+    return false;
+  }
+  return true;
+}
+
 void Grid::addCell(std::unique_ptr<Cell> cell, int track)
 {
   if (track >= layouts_.size()) {
@@ -226,6 +240,16 @@ int Grid::numLayouts() const
   return layouts_.size();
 }
 
+int Grid::getLayoutWidth(int index) const
+{
+  return layouts_[index]->getWidth();
+}
+
+int Grid::getLayoutHeight(int index) const
+{
+  return layouts_[index]->getHeight();
+}
+
 int Grid::getRowWidth() const
 {
   int row_width = 0;

src/ram/src/layout.h

@@ -82,6 +82,8 @@ class Grid
 
   void addLayout(std::unique_ptr<Layout> layout);
 
+  bool insertLayout(std::unique_ptr<Layout> layout, int index);
+
   void addCell(std::unique_ptr<Cell> cell, int track);
 
   void gridInit();
@@ -96,6 +98,10 @@ class Grid
 
   int numLayouts() const;
 
+  int getLayoutWidth(int index) const;
+
+  int getLayoutHeight(int index) const;
+
   int getRowWidth() const;
 
  private:

src/ram/src/ram.cpp

@@ -173,6 +173,22 @@ void RamGen::makeCellByte(Grid& ram_grid,
   ram_grid.addCell(std::move(sel_cell), (byte_number * 9) + 8);
 }
 
+std::unique_ptr<Layout> RamGen::generateTapColumn(const int word_count,
+                                                  const int tapcell_col)
+{
+  auto tapcell_layout = std::make_unique<Layout>(odb::vertical);
+  for (int i = 0; i <= word_count; ++i) {
+    auto tapcell_cell = std::make_unique<Cell>();
+    makeCellInst(tapcell_cell.get(),
+                 "tapcell",
+                 fmt::format("cell{}_{}", tapcell_col, i),
+                 tapcell_,
+                 {});
+    tapcell_layout->addCell(std::move(tapcell_cell));
+  }
+  return tapcell_layout;
+}
+
 std::unique_ptr<Cell> RamGen::makeDecoder(
     const std::string& prefix,
     const int num_word,
@@ -371,7 +387,9 @@ void RamGen::generate(const int bytes_per_word,
                       const int read_ports,
                       dbMaster* storage_cell,
                       dbMaster* tristate_cell,
-                      dbMaster* inv_cell)
+                      dbMaster* inv_cell,
+                      dbMaster* tapcell,
+                      int max_tap_dist)
 {
   const int bits_per_word = bytes_per_word * 8;
   const std::string ram_name
@@ -382,6 +400,7 @@ void RamGen::generate(const int bytes_per_word,
   storage_cell_ = storage_cell;
   tristate_cell_ = tristate_cell;
   inv_cell_ = inv_cell;
+  tapcell_ = tapcell;
   and2_cell_ = nullptr;
   clock_gate_cell_ = nullptr;
   buffer_cell_ = nullptr;
@@ -503,40 +522,40 @@ void RamGen::generate(const int bytes_per_word,
     }
 
     for (int bit = 0; bit < 8; ++bit) {
-      auto buffer_cell = std::make_unique<Cell>();
-      makeCellInst(buffer_cell.get(),
+      auto buffer_grid_cell = std::make_unique<Cell>();
+      makeCellInst(buffer_grid_cell.get(),
                    "buffer",
                    fmt::format("in[{}]", bit),
                    buffer_cell_,
                    {{"A", D_bTerms[bit]->getNet()}, {"X", D_nets[bit]}});
-      ram_grid.addCell(std::move(buffer_cell), bit);
+      ram_grid.addCell(std::move(buffer_grid_cell), bit);
     }
   }
 
   auto cell_inv_layout = std::make_unique<Layout>(odb::vertical);
   // check for AND gate, specific case for 2 words
   if (num_inputs > 1) {
     for (int i = num_inputs - 1; i >= 0; --i) {
-      auto inv_cell = std::make_unique<Cell>();
-      makeCellInst(inv_cell.get(),
+      auto inv_grid_cell = std::make_unique<Cell>();
+      makeCellInst(inv_grid_cell.get(),
                    "decoder",
                    fmt::format("inv_{}", i),
                    inv_cell_,
                    {{"A", addr[i]->getNet()}, {"Y", inv_addr[i]}});
-      cell_inv_layout->addCell(std::move(inv_cell));
+      cell_inv_layout->addCell(std::move(inv_grid_cell));
       for (int filler_count = 0; filler_count < num_inputs - 1;
            ++filler_count) {
         cell_inv_layout->addCell(nullptr);
       }
     }
   } else {
-    auto inv_cell = std::make_unique<Cell>();
-    makeCellInst(inv_cell.get(),
+    auto inv_grid_cell = std::make_unique<Cell>();
+    makeCellInst(inv_grid_cell.get(),
                  "decoder",
                  fmt::format("inv_{}", 0),
                  inv_cell_,
                  {{"A", addr[0]->getNet()}, {"Y", inv_addr[0]}});
-    cell_inv_layout->addCell(std::move(inv_cell));
+    cell_inv_layout->addCell(std::move(inv_grid_cell));
   }
 
   ram_grid.addLayout(std::move(cell_inv_layout));
@@ -546,6 +565,38 @@ void RamGen::generate(const int bytes_per_word,
   ram_grid.setOrigin(ram_origin);
   ram_grid.gridInit();
 
+  if (tapcell_) {
+    // max tap distance specified is greater than the length of ram
+    if (ram_grid.getRowWidth() <= max_tap_dist) {
+      auto tapcell_layout = generateTapColumn(word_count, 0);
+      ram_grid.insertLayout(std::move(tapcell_layout), 0);
+    } else {
+      // needed this calculation so first cells have right distance
+      int nearest_tap
+          = (max_tap_dist / ram_grid.getWidth()) * ram_grid.getLayoutWidth(0);
+      int tapcell_count = 0;
+      // iterates through each of the columns
+      for (int col = 0; col < ram_grid.numLayouts(); ++col) {
+        if (nearest_tap + ram_grid.getLayoutWidth(col) >= max_tap_dist) {
+          // if the nearest_tap is too far, generate tap column
+          auto tapcell_layout = generateTapColumn(word_count, tapcell_count);
+          ram_grid.insertLayout(std::move(tapcell_layout), col);
+          ++col;  // col adjustment after insertion
+          nearest_tap = 0;
+          ++tapcell_count;
+        }
+        nearest_tap += ram_grid.getLayoutWidth(col);
+      }
+      // check for last column in the grid
+      if (nearest_tap >= max_tap_dist) {
+        auto tapcell_layout = generateTapColumn(word_count, tapcell_count);
+        ram_grid.addLayout(std::move(tapcell_layout));
+      }
+    }
+  }
+
+  ram_grid.gridInit();
+
   auto db_libs = db_->getLibs().begin();
   auto db_sites = *(db_libs->getSites().begin());
   auto sites_width = db_sites->getWidth();

src/ram/src/ram.i

@@ -20,7 +20,9 @@ generate_ram_netlist_cmd(int bytes_per_word,
                          const char* storage_cell_name,
                          const char* tristate_cell_name,
                          const char* inv_cell_name,
-                         const int read_ports)
+                         const int read_ports,
+                         const char* tapcell_name,
+                         const int max_tap_dist)
 {
   auto* app = ord::OpenRoad::openRoad();
   auto* ram_gen = app->getRamGen();
@@ -58,8 +60,21 @@ generate_ram_netlist_cmd(int bytes_per_word,
                               inv_cell_name);
     }
   }
+
+  odb::dbMaster* tapcell = nullptr;
+  if (tapcell_name[0] != '\0') {
+    tapcell = db->findMaster(tapcell_name);
+    if (!tapcell) {
+      app->getLogger()->error(utl::RAM,
+                              19,
+                              "Tapcell {} can't be found",
+                              tapcell_name);
+    }
+  }
+
   ram_gen->generate(bytes_per_word, word_count, read_ports,
-                    storage_cell, tristate_cell, inv_cell);
+                    storage_cell, tristate_cell, inv_cell, tapcell,
+                    max_tap_dist);
 }
 
 } //namespace_ram

src/ram/src/ram.tcl

@@ -6,12 +6,14 @@ sta::define_cmd_args "generate_ram_netlist" {-bytes_per_word bits
                                              [-storage_cell name]
                                              [-tristate_cell name]
                                              [-inv_cell name]
-                                             [-read_ports count]}
+                                             [-read_ports count]
+                                             [-tapcell name]
+                                             [-max_tap_dist value]}
 
 proc generate_ram_netlist { args } {
   sta::parse_key_args "generate_ram_netlist" args \
-    keys {-bytes_per_word -word_count -storage_cell -tristate_cell -inv_cell
-      -read_ports } flags {}
+    keys { -bytes_per_word -word_count -storage_cell -tristate_cell -inv_cell
+      -read_ports -tapcell -max_tap_dist } flags {}
 
   if { [info exists keys(-bytes_per_word)] } {
     set bytes_per_word $keys(-bytes_per_word)
@@ -45,8 +47,23 @@ proc generate_ram_netlist { args } {
     set read_ports $keys(-read_ports)
   }
 
+  set tapcell ""
+  set max_tap_dist 0
+  if { [info exists keys(-tapcell)] } {
+    if { [info exists keys(-max_tap_dist)] } {
+      set max_tap_dist $keys(-max_tap_dist)
+      set max_tap_dist [ord::microns_to_dbu $max_tap_dist]
+    } else {
+      utl::error RAM 21 "The -max_tap_dist argument must be specified with tapcell."
+    }
+    set tapcell $keys(-tapcell)
+  } else {
+    utl::warn RAM 22 "No tapcell is specified.
+        The generated layout may not pass Design Rule Checks."
+  }
+
   ram::generate_ram_netlist_cmd $bytes_per_word $word_count $storage_cell \
-    $tristate_cell $inv_cell $read_ports
+    $tristate_cell $inv_cell $read_ports $tapcell $max_tap_dist
 }
 
 sta::define_cmd_args "generate_ram" {-bytes_per_word bits
@@ -60,13 +77,16 @@ sta::define_cmd_args "generate_ram" {-bytes_per_word bits
                                      -routing_layer config
                                      -ver_layer config
                                      -hor_layer config
-                                     -filler_cells fillers}
+                                     -filler_cells fillers
+                                     [-tapcell name]
+                                     [-max_tap_dist value]}
 
 # user arguments for generate ram arguments
 proc generate_ram { args } {
   sta::parse_key_args "generate_ram" args \
-    keys {-bytes_per_word -word_count -storage_cell -tristate_cell -inv_cell -read_ports
-      -power_pin -ground_pin -routing_layer -ver_layer -hor_layer -filler_cells} flags {}
+    keys { -bytes_per_word -word_count -storage_cell -tristate_cell -inv_cell -read_ports
+      -power_pin -ground_pin -routing_layer -ver_layer -hor_layer -filler_cells
+        -tapcell -max_tap_dist} flags {}
 
   sta::check_argc_eq0 "generate_ram" $args
 
@@ -95,6 +115,14 @@ proc generate_ram { args } {
     lappend ram_netlist_args -inv_cell $keys(-inv_cell)
   }
 
+  if { [info exists keys(-tapcell)] } {
+    lappend ram_netlist_args -tapcell $keys(-tapcell)
+  }
+
+  if { [info exists keys(-max_tap_dist)] } {
+    lappend ram_netlist_args -max_tap_dist $keys(-max_tap_dist)
+  }
+
   generate_ram_netlist {*}$ram_netlist_args
 
   ord::design_created