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1 parent 55cb3a6 commit 4bdce0eCopy full SHA for 4bdce0e
src/cts/test/gated_clock4.ok
@@ -312,6 +312,4 @@ delta HPWL 49070 %
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[DEBUG CTS-insertion delay] new delay buffer delaybuf_7_core is inserted at (956131 1966825)
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[INFO CTS-0036] inserted 8 delay buffers
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[INFO CTS-0037] Total number of delay buffers: 8
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-Differences found at line 4.
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- wire delaynet_3_core;
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- wire delaynet_4_core;
+No differences found.
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