@@ -62,19 +62,22 @@ using cut::LogicCut;
6262using cut::LogicExtractorFactory;
6363using ::testing::Contains;
6464
65- std::once_flag init_abc_flag;
65+ static std::once_flag init_abc_flag;
66+
67+ static const std::string prefix (" _main/src/cut/test/" );
6668
6769class AbcTest : public tst ::Fixture
6870{
6971 protected:
7072 void SetUp () override
7173 {
7274 std::call_once (init_abc_flag, []() { abc::Abc_Start (); });
73- library_ = readLiberty (" ./ Nangate45/Nangate45_typ.lib" );
75+ library_ = readLiberty (prefix + " Nangate45/Nangate45_typ.lib" );
7476
7577 odb::dbTech* tech
76- = loadTechLef (" nangate45" , " ./Nangate45/Nangate45_tech.lef" );
77- loadLibaryLef (tech, " nangate45" , " ./Nangate45/Nangate45_stdcell.lef" );
78+ = loadTechLef (" nangate45" , prefix + " Nangate45/Nangate45_tech.lef" );
79+ loadLibaryLef (
80+ tech, " nangate45" , prefix + " Nangate45/Nangate45_stdcell.lef" );
7881
7982 sta::Units* units = library_->units ();
8083 power_unit_ = units->powerUnit ();
@@ -87,7 +90,7 @@ class AbcTest : public tst::Fixture
8790 ord::dbVerilogNetwork verilog_network (sta_.get ());
8891
8992 sta::VerilogReader verilog_reader (&verilog_network);
90- verilog_reader.read (file_name.c_str ());
93+ verilog_reader.read (getFilePath ( file_name) .c_str ());
9194
9295 ord::dbLinkDesign (top.c_str (),
9396 &verilog_network,
@@ -143,11 +146,11 @@ class AbcTestSky130 : public AbcTest
143146 {
144147 std::call_once (init_abc_flag, []() { abc::Abc_Start (); });
145148
146- library_ = readLiberty (" ./ sky130/sky130_fd_sc_hd__ss_n40C_1v40.lib" );
149+ library_ = readLiberty (prefix + " sky130/sky130_fd_sc_hd__ss_n40C_1v40.lib" );
147150
148- odb::dbTech* tech = loadTechLef (" sky130" , " ./ sky130/sky130hd.tlef" );
149- odb::dbLib* lib
150- = loadLibaryLef ( tech, " sky130" , " ./ sky130/sky130hd_std_cell.lef" );
151+ odb::dbTech* tech = loadTechLef (" sky130" , prefix + " sky130/sky130hd.tlef" );
152+ odb::dbLib* lib = loadLibaryLef (
153+ tech, " sky130" , prefix + " sky130/sky130hd_std_cell.lef" );
151154
152155 sta_->postReadLef (tech, lib);
153156
@@ -163,20 +166,20 @@ class AbcTestAsap7 : public AbcTest
163166 std::call_once (init_abc_flag, []() { abc::Abc_Start (); });
164167
165168 std::array<const char *, 5 > liberty_paths
166- = {" ./ asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz" ,
167- " ./ asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz" ,
168- " ./ asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz" ,
169- " ./ asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib" ,
170- " ./ asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz" };
169+ = {" asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz" ,
170+ " asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz" ,
171+ " asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz" ,
172+ " asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib" ,
173+ " asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz" };
171174
172175 for (const char * liberty_path : liberty_paths) {
173- library_ = readLiberty (liberty_path);
176+ library_ = readLiberty (prefix + liberty_path);
174177 }
175178
176179 odb::dbTech* tech
177- = loadTechLef (" asap7" , " ./ asap7/asap7_tech_1x_201209.lef" );
180+ = loadTechLef (" asap7" , prefix + " asap7/asap7_tech_1x_201209.lef" );
178181 odb::dbLib* lib = loadLibaryLef (
179- tech, " asap7" , " ./ asap7/asap7sc7p5t_28_R_1x_220121a.lef" );
182+ tech, " asap7" , prefix + " asap7/asap7sc7p5t_28_R_1x_220121a.lef" );
180183
181184 sta_->postReadLef (tech, lib);
182185
@@ -353,7 +356,7 @@ TEST_F(AbcTest, ExtractsAndGateCorrectly)
353356 factory.AddDbSta (sta_.get ());
354357 AbcLibrary abc_library = factory.Build ();
355358
356- LoadVerilog (" simple_and_gate_extract.v" );
359+ LoadVerilog (prefix + " simple_and_gate_extract.v" );
357360
358361 sta::dbNetwork* network = sta_->getDbNetwork ();
359362 sta::Vertex* flop_input_vertex = nullptr ;
@@ -378,7 +381,7 @@ TEST_F(AbcTest, ExtractsEmptyCutSetCorrectly)
378381 factory.AddDbSta (sta_.get ());
379382 AbcLibrary abc_library = factory.Build ();
380383
381- LoadVerilog (" empty_cut_set.v" );
384+ LoadVerilog (prefix + " empty_cut_set.v" );
382385
383386 sta::dbNetwork* network = sta_->getDbNetwork ();
384387 sta::Vertex* flop_input_vertex = nullptr ;
@@ -402,7 +405,7 @@ TEST_F(AbcTest, ExtractSideOutputsCorrectly)
402405 factory.AddDbSta (sta_.get ());
403406 AbcLibrary abc_library = factory.Build ();
404407
405- LoadVerilog (" side_outputs_extract.v" );
408+ LoadVerilog (prefix + " side_outputs_extract.v" );
406409
407410 sta::dbNetwork* network = sta_->getDbNetwork ();
408411 sta::Vertex* flop_input_vertex = nullptr ;
@@ -433,7 +436,7 @@ TEST_F(AbcTest, BuildAbcMappedNetworkFromLogicCut)
433436 factory.AddDbSta (sta_.get ());
434437 AbcLibrary abc_library = factory.Build ();
435438
436- LoadVerilog (" side_outputs_extract_logic_depth.v" );
439+ LoadVerilog (prefix + " side_outputs_extract_logic_depth.v" );
437440
438441 sta::dbNetwork* network = sta_->getDbNetwork ();
439442 sta::Vertex* flop_input_vertex = nullptr ;
@@ -479,7 +482,7 @@ TEST_F(AbcTest, BuildComplexLogicCone)
479482 factory.AddDbSta (sta_.get ());
480483 AbcLibrary abc_library = factory.Build ();
481484
482- LoadVerilog (" aes_nangate45.v" , /* top=*/ " aes_cipher_top" );
485+ LoadVerilog (prefix + " aes_nangate45.v" , /* top=*/ " aes_cipher_top" );
483486
484487 sta::dbNetwork* network = sta_->getDbNetwork ();
485488 sta::Vertex* flop_input_vertex = nullptr ;
@@ -503,7 +506,7 @@ TEST_F(AbcTest, InsertingMappedLogicCutDoesNotThrow)
503506 factory.AddDbSta (sta_.get ());
504507 AbcLibrary abc_library = factory.Build ();
505508
506- LoadVerilog (" aes_nangate45.v" , /* top=*/ " aes_cipher_top" );
509+ LoadVerilog (prefix + " aes_nangate45.v" , /* top=*/ " aes_cipher_top" );
507510
508511 sta::dbNetwork* network = sta_->getDbNetwork ();
509512 sta::Vertex* flop_input_vertex = nullptr ;
@@ -533,7 +536,7 @@ TEST_F(AbcTest,
533536 factory.AddDbSta (sta_.get ());
534537 AbcLibrary abc_library = factory.Build ();
535538
536- LoadVerilog (" side_outputs_extract_logic_depth.v" );
539+ LoadVerilog (prefix + " side_outputs_extract_logic_depth.v" );
537540
538541 sta::dbNetwork* network = sta_->getDbNetwork ();
539542 sta::Vertex* flop_input_vertex = nullptr ;
@@ -595,7 +598,7 @@ TEST_F(AbcTestSky130, EnsureThatSky130MultiOutputConstCellsAreMapped)
595598 factory.AddDbSta (sta_.get ());
596599 AbcLibrary abc_library = factory.Build ();
597600
598- LoadVerilog (" sky130_const_cell.v" );
601+ LoadVerilog (prefix + " sky130_const_cell.v" );
599602
600603 sta::dbNetwork* network = sta_->getDbNetwork ();
601604 sta::Instance* flop_input_instance = network->findInstance (" _403_" );
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