test/orfs/mock-array: verilator config test, disabled by default

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

test/orfs/mock-array/BUILD

@@ -1,5 +1,5 @@
 load("@bazel-orfs//:openroad.bzl", "orfs_run")
-load("@bazel-orfs//toolchains/scala:chisel.bzl", "chisel_binary")
+load("@bazel-orfs//toolchains/scala:chisel.bzl", "chisel_binary", "chisel_test")
 load("//test/orfs/asap7:asap7.bzl", "ASAP7_REMOVE_CELLS")
 load(":mock-array.bzl", "config", "element", "mock_array", "verilog")
 
@@ -139,3 +139,12 @@ orfs_run(
         "Element_4x4",
     ]
 ]
+
+# Used to validate Verilator dependency; verilator is used for
+# simulation of MockArray.
+chisel_test(
+    name = "TinyAdder_test",
+    srcs = ["src/test/scala/TinyAdderTest.scala"],
+    tags = ["manual"],
+    deps = [],
+)

test/orfs/mock-array/src/test/scala/TinyAdderTest.scala

@@ -0,0 +1,33 @@
+import chisel3._
+import java.io.File
+
+import chisel3._
+import chisel3.experimental.BundleLiterals._
+import chisel3.simulator.scalatest.ChiselSim
+import org.scalatest.freespec.AnyFreeSpec
+import org.scalatest.matchers.must.Matchers
+
+class TinyAdder extends Module {
+  val io = IO(new Bundle {
+    val a = Input(UInt(8.W))
+    val b = Input(UInt(8.W))
+    val out = Output(UInt(8.W))
+  })
+  io.out := io.a + io.b
+}
+
+class TinyAdderTests extends AnyFreeSpec with Matchers with ChiselSim {
+  "add" in {
+    simulate(new TinyAdder()) { dut =>
+      dut.reset.poke(true.B)
+      dut.clock.step()
+      dut.reset.poke(false.B)
+      dut.clock.step()
+
+      dut.io.a.poke(30.U)
+      dut.io.b.poke(12.U)
+      dut.clock.step()
+      dut.io.out.expect(42.U)
+    }
+  }
+}