Merge pull request #366 from The-OpenROAD-Project/resizer

write_verilog vdd/vss port dcls

Author: jjcherry56

src/OpenSTA

@@ -1,6 +1,4 @@
-###############################################################################
 # reg1.v
-###############################################################################
 
 VERSION 5.8 ; 
 NAMESCASESENSITIVE ON ;

src/dbSta/test/reg1.def

@@ -21,4 +21,5 @@ record_tests {
   write_verilog2
   write_verilog3
   write_verilog4
+  write_verilog5
 }

src/dbSta/test/regression_tests.tcl

@@ -0,0 +1,36 @@
+VERSION 5.8 ; 
+NAMESCASESENSITIVE ON ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+
+DESIGN top ;
+
+UNITS DISTANCE MICRONS 1000 ;
+
+DIEAREA ( 0 0 ) ( 1000 1000 ) ;
+
+
+COMPONENTS 5 ;
+- u1 BUF_X1 ;
+END COMPONENTS
+
+PINS 4 ;
+- in1 + NET in1 + DIRECTION INPUT ;
+- out1 + NET out + DIRECTION OUTPUT ;
+- VDD + NET VDD + DIRECTION INPUT + USE POWER ;
+- VSS + NET VSS + DIRECTION INPUT + USE GROUND ;
+END PINS
+
+SPECIALNETS 2 ;
+- VSS  ( * VSS )
+  + USE GROUND ;
+- VDD  ( * VDD )
+  + USE POWER ;
+END SPECIALNETS
+
+NETS 2 ;
+- in1 ( PIN in1 ) ( u1 A ) ;
+- out1 ( u1 Z ) ( PIN out1 ) ;
+END NETS
+
+END DESIGN

src/dbSta/test/write_verilog5.def

@@ -0,0 +1,27 @@
+Notice 0: Reading LEF file:  Nangate45/Nangate45.lef
+Notice 0:     Created 22 technology layers
+Notice 0:     Created 27 technology vias
+Notice 0:     Created 134 library cells
+Notice 0: Finished LEF file:  Nangate45/Nangate45.lef
+Notice 0: 
+Reading DEF file: write_verilog5.def
+Notice 0: Design: top
+Notice 0:     Created 4 pins.
+Notice 0:     Created 1 components and 4 component-terminals.
+Notice 0:     Created 2 special nets and 2 connections.
+Notice 0:     Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: write_verilog5.def
+module top (in1,
+    out1,
+    VDD,
+    VSS);
+ input in1;
+ output out1;
+ input VDD;
+ input VSS;
+
+ BUF_X1 u1 (.A(in1),
+    .Z(out1),
+    .VDD(VDD),
+    .VSS(VSS));
+endmodule

src/dbSta/test/write_verilog5.ok

@@ -0,0 +1,9 @@
+# write_verilog vdd/vss def pins
+source "helpers.tcl"
+read_lef Nangate45/Nangate45.lef
+read_liberty Nangate45/Nangate45_typ.lib
+read_def write_verilog5.def
+
+set verilog_file [make_result_file write_verilog5.v]
+write_verilog -sort $verilog_file
+report_file $verilog_file