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Merge pull request #8678 from The-OpenROAD-Project-staging/dbsta-original-name
dbSta: save the original name of a module in "original_name" string prop
2 parents a3cdbd7 + 4f74c40 commit 5ba8849

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3 files changed

+13
-2
lines changed

3 files changed

+13
-2
lines changed

src/dbSta/src/dbReadVerilog.cc

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
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#include <odb/dbSet.h>
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#include <cstddef>
9+
#include <cstring>
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#include <fstream>
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#include <map>
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#include <memory>
@@ -368,9 +369,12 @@ void Verilog2db::makeDbModule(
368369
if (parent == nullptr) {
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module = block_->getTopModule();
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} else {
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const char* name = network_->name(cell);
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// This uniquifies the cell
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module = dbModule::makeUniqueDbModule(
373-
network_->name(cell), network_->name(inst), block_);
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module = dbModule::makeUniqueDbModule(name, network_->name(inst), block_);
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if (strcmp(name, module->getName()) != 0) {
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odb::dbStringProperty::create(module, "original_name", name);
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}
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registerHierModule(module);
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src/dbSta/test/read_verilog10.ok

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,3 +9,4 @@ b2/r1 snl_ffqx1
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b2/u1 snl_bufx1
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b2/u2 snl_bufx1
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Found filename prop src_file_0 on block
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block1_b2 block1

src/dbSta/test/read_verilog10.tcl

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,3 +29,9 @@ if { $found_prop != 0 } {
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} else {
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error "Didn't find filename prop on block"
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}
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foreach module [$block getModules] {
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set prop [odb::dbStringProperty_find $module "original_name"]
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if { $prop != "NULL" } {
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puts "[$module getName] [$prop getValue]"
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}
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}

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