Merge pull request #2714 from macd/pdn-python

Python wrapper for pdn and core set of regression tests

Author: maliberty

include/ord/Design.h

@@ -113,6 +113,10 @@ namespace psm {
 class PDNSim;
 }
 
+namespace pdn {
+class PdnGen;
+}
+
 namespace ord {
 
 class Tech;
@@ -160,6 +164,7 @@ class Design
   rmp::Restructure* getRestructure();
   stt::SteinerTreeBuilder* getSteinerTreeBuilder();
   psm::PDNSim* getPDNSim();
+  pdn::PdnGen* getPdnGen();
 
  private:
   Tech* tech_;

src/CMakeLists.txt

@@ -399,6 +399,7 @@ if (Python3_FOUND AND BUILD_PYTHON)
     rmp_py
     stt_py
     psm_py
+    pdn_py
   )
 else()
   message(STATUS "Python3 disabled")

src/Design.cc

@@ -240,4 +240,10 @@ psm::PDNSim* Design::getPDNSim()
   return app->getPDNSim();
 }
 
+pdn::PdnGen* Design::getPdnGen()
+{
+  auto app = OpenRoad::openRoad();
+  return app->getPdnGen();
+}
+
 }  // namespace ord

src/Main.cc

@@ -98,6 +98,7 @@ using std::string;
   X(rmp)                                 \
   X(stt)                                 \
   X(psm)                                 \
+  X(pdn)                                 \
   X(odb)
 
 #define FOREACH_TOOL(X)            \

src/odb/src/swig/python/dbtypes.i

@@ -217,7 +217,6 @@
 
 // Handle return by ref.
 %apply int &OUTPUT { int & overhang1, int & overhang2 };
-%apply int &OUTPUT { int & x, int & y };
 %apply int &OUTPUT { int & x_spacing, int & y_spacing };
 WRAP_OBJECT_RETURN_REF(odb::Rect, r)
 WRAP_OBJECT_RETURN_REF(odb::Rect, rect)

src/pdn/include/pdn/PdnGen.hh

@@ -38,7 +38,6 @@
 #include <array>
 #include <map>
 #include <memory>
-#include <regex>
 
 #include "odb/db.h"
 #include "utl/Logger.h"
@@ -57,8 +56,6 @@ using odb::dbRegion;
 
 using utl::Logger;
 
-using std::regex;
-
 enum ExtensionMode
 {
   CORE,

src/pdn/src/CMakeLists.txt

@@ -80,3 +80,29 @@ messages(
   TARGET pdn
   OUTPUT_DIR ..
 )
+
+if (Python3_FOUND AND BUILD_PYTHON)
+  swig_lib(NAME          pdn_py
+           NAMESPACE     pdn
+           LANGUAGE      python
+           I_FILE        PdnGen-py.i
+           SWIG_INCLUDES ${ODB_HOME}/src/swig/common
+                         ${ODB_HOME}/src/swig/python
+                         ${ODB_HOME}/include
+                         ${PROJECT_SOURCE_DIR}/../include/pdn
+           SCRIPTS       ${CMAKE_CURRENT_BINARY_DIR}/pdn_py.py
+  )
+
+  target_include_directories(pdn_py
+    PUBLIC
+      .
+  )
+  
+  target_link_libraries(pdn_py
+    PUBLIC
+      pdn
+      odb
+      gui
+    )
+
+endif()

src/pdn/src/PdnGen-py.i

@@ -0,0 +1,101 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2023, The Regents of the University of California
+// All rights reserved.
+//
+// BSD 3-Clause License
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// * Redistributions of source code must retain the above copyright notice, this
+//   list of conditions and the following disclaimer.
+//
+// * Redistributions in binary form must reproduce the above copyright notice,
+//   this list of conditions and the following disclaimer in the documentation
+//   and/or other materials provided with the distribution.
+//
+// * Neither the name of the copyright holder nor the names of its
+//   contributors may be used to endorse or promote products derived from
+//   this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+///////////////////////////////////////////////////////////////////////////////
+%module pdngen
+%{
+
+// These includes are needed by the SWIG generated CXX files mostly 
+// for determining the size of Classes that they define. Since that are
+// not actually wrapped, the classes defined in these files will appear as
+// opaque pointers in Python.
+#include "../src/connect.h"
+#include "../src/domain.h"
+#include "../src/grid.h"
+#include "../src/power_cells.h"
+#include "../src/renderer.h"
+
+#include "pdn/PdnGen.hh"
+#include "odb/db.h"
+#include <array>
+#include <string>
+#include <memory>
+#include <vector>
+
+using pdn::ExtensionMode;
+using namespace pdn;
+ 
+%}
+
+%include <std_vector.i>
+%include <std_array.i>
+%include <std_map.i>
+
+// this maps unsigned long to the enum ExtensionMode
+%include typemaps.i
+%apply unsigned long { ExtensionMode };
+
+%import "odb.i"
+%import "dbtypes.i"
+%include <std_string.i>
+
+// These are needed to coax swig into sending or returning Python 
+// lists, arrays, or sets (as appropriate) of opaque pointers. Note 
+// that you must %include (not %import) <std_vector.i> and <std_array.i> 
+// before these definitions
+namespace std {
+  %template(split_cuts_stuff) std::vector<int>;
+  %template(stuff)        std::array<int, 4>;
+  %template(split_map)    std::map<odb::dbTechLayer *, int>;  
+  %template(grid_list)    std::vector<pdn::Grid *>;
+  %template(domain_list)  std::vector<pdn::VoltageDomain *>;
+  %template(net_list)     std::vector<odb::dbNet *>;
+  %template(viagen_list)  std::vector<odb::dbTechViaGenerateRule *>;
+  %template(techvia_list) std::vector<odb::dbTechVia *>;
+  %template(layer_list)   std::vector<odb::dbTechLayer *>;
+}
+
+%include "../../Exception-py.i"
+%include "pdn/PdnGen.hh"
+
+%inline %{
+
+namespace pdn {
+
+// difficult to pass a set. repair_pdn_via takes a vector and then
+// rebuilds the set in C++, so we just borrow that here.
+void repair_pdn_vias(const std::vector<odb::dbNet*>& nets);
+ 
+}  // namespace
+
+%} //  %inline

src/pdn/test/asap7_taper.py

@@ -0,0 +1,32 @@
+# test for via stacks that require a taper due to min width rules
+from openroad import Design, Tech
+import pdn_aux
+import helpers
+
+tech = Tech()
+tech.readLef("asap7_vias/asap7_tech_1x.lef")
+tech.readLef("asap7_vias/asap7sc7p5t_27_R_1x.lef")
+
+design = Design(tech)
+design.readDef("asap7_vias/floorplan.def")
+
+pdn_aux.add_global_connection(design, net_name="VDD", pin_pattern="^VDD$", power=True)
+pdn_aux.add_global_connection(design, net_name="VSS", pin_pattern="^VSS$", ground=True)
+
+pdn_aux.set_voltage_domain(design, power="VDD", ground="VSS")
+pdn_aux.define_pdn_grid_real(design, name="top", voltage_domains=["Core"])
+
+pdn_aux.add_pdn_stripe(design, grid="top", layer="M1", width=0.018, pitch=0.54, offset=0, followpins=True)
+pdn_aux.add_pdn_stripe(design, grid="top", layer="M2", width=0.018, pitch=0.54, offset=0, followpins=True)
+pdn_aux.add_pdn_stripe(design, grid="top", layer="M5", width=0.12,  spacing=0.072, pitch=11.88, offset=0.300)
+pdn_aux.add_pdn_stripe(design, grid="top", layer="M6", width=0.288, spacing=0.096, pitch=12.0, offset=0.513)
+
+pdn_aux.add_pdn_connect(design, grid="top", layers=["M1", "M2"])
+pdn_aux.add_pdn_connect(design, grid="top", layers=["M2", "M5"])
+pdn_aux.add_pdn_connect(design, grid="top", layers=["M5", "M6"])
+
+pdn_aux.pdngen_db(design)
+
+def_file = helpers.make_result_file("asap7_taper.def")
+design.writeDef(def_file)
+helpers.diff_files("asap7_taper.defok", def_file)

src/pdn/test/core_grid.py

@@ -0,0 +1,26 @@
+# test for pdngen -reset
+from openroad import Design, Tech
+import pdn_aux
+import helpers
+
+tech = Tech()
+tech.readLef("Nangate45/Nangate45_tech.lef")
+tech.readLef("Nangate45/Nangate45_stdcell.lef")
+
+design = Design(tech)
+design.readDef("nangate_gcd/floorplan.def")
+pdngen = design.getPdnGen()
+
+pdn_aux.add_global_connection(design, net_name="VDD", pin_pattern="VDD", power=True)
+pdn_aux.add_global_connection(design, net_name="VSS", pin_pattern="VSS", ground=True)
+
+pdn_aux.set_voltage_domain(design, power='VDD', ground='VSS')
+
+pdn_aux.define_pdn_grid_real(design, name="Core")
+pdn_aux.add_pdn_stripe(design, followpins=True, layer="metal1")
+
+pdn_aux.pdngen_db(design)
+
+def_file = helpers.make_result_file("core_grid.def")
+design.writeDef(def_file)
+helpers.diff_files("core_grid.defok", def_file)