|
6 | 6 | [INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 |
7 | 7 | [INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 |
8 | 8 | [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 |
| 9 | +[INFO PDN-0001] Inserting grid: ram_grid |
| 10 | +Found 0 macro blocks. |
| 11 | +Using 2 tracks default min distance between IO pins. |
| 12 | +[INFO PPL-0067] Restrict pins [ D[0] D[1] D[2] D[3] D[4] ... ] to region 0.00u-120.52u at the TOP edge. |
| 13 | +[INFO PPL-0001] Number of available slots 280 |
| 14 | +[INFO PPL-0002] Number of I/O 29 |
| 15 | +[INFO PPL-0003] Number of I/O w/sink 29 |
| 16 | +[INFO PPL-0004] Number of I/O w/o sink 0 |
| 17 | +[INFO PPL-0005] Slots per section 200 |
| 18 | +[INFO PPL-0008] Successfully assigned pins to sections. |
| 19 | +[INFO PPL-0012] I/O nets HPWL: 514.11 um. |
| 20 | +[INFO DPL-0001] Placed 48 filler instances. |
| 21 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon |
| 22 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon |
| 23 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via |
| 24 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via |
| 25 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 |
| 26 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 |
| 27 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 |
| 28 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 |
| 29 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 |
| 30 | +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 |
| 31 | +[INFO DRT-0167] List of default vias: |
| 32 | + Layer mcon |
| 33 | + default via: L1M1_PR |
| 34 | + Layer via |
| 35 | + default via: M1M2_PR |
| 36 | + Layer via2 |
| 37 | + default via: M2M3_PR |
| 38 | + Layer via3 |
| 39 | + default via: M3M4_PR |
| 40 | + Layer via4 |
| 41 | + default via: M4M5_PR |
| 42 | +[INFO DRT-0168] Init region query. |
| 43 | +[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. |
| 44 | +[INFO DRT-0033] FR_VIA shape region query size = 0. |
| 45 | +[INFO DRT-0033] li1 shape region query size = 7683. |
| 46 | +[INFO DRT-0033] mcon shape region query size = 256. |
| 47 | +[INFO DRT-0033] met1 shape region query size = 1082. |
| 48 | +[INFO DRT-0033] via shape region query size = 30. |
| 49 | +[INFO DRT-0033] met2 shape region query size = 78. |
| 50 | +[INFO DRT-0033] via2 shape region query size = 6. |
| 51 | +[INFO DRT-0033] met3 shape region query size = 17. |
| 52 | +[INFO DRT-0033] via3 shape region query size = 0. |
| 53 | +[INFO DRT-0033] met4 shape region query size = 0. |
| 54 | +[INFO DRT-0033] via4 shape region query size = 0. |
| 55 | +[INFO DRT-0033] met5 shape region query size = 0. |
| 56 | +[INFO DRT-0178] Init guide query. |
| 57 | +[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. |
| 58 | +[INFO DRT-0036] FR_VIA guide region query size = 0. |
| 59 | +[INFO DRT-0036] li1 guide region query size = 457. |
| 60 | +[INFO DRT-0036] mcon guide region query size = 0. |
| 61 | +[INFO DRT-0036] met1 guide region query size = 325. |
| 62 | +[INFO DRT-0036] via guide region query size = 0. |
| 63 | +[INFO DRT-0036] met2 guide region query size = 82. |
| 64 | +[INFO DRT-0036] via2 guide region query size = 0. |
| 65 | +[INFO DRT-0036] met3 guide region query size = 26. |
| 66 | +[INFO DRT-0036] via3 guide region query size = 0. |
| 67 | +[INFO DRT-0036] met4 guide region query size = 0. |
| 68 | +[INFO DRT-0036] via4 guide region query size = 0. |
| 69 | +[INFO DRT-0036] met5 guide region query size = 0. |
| 70 | +[INFO DRT-0179] Init gr pin query. |
| 71 | +No differences found. |
9 | 72 | No differences found. |
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