rsz: Enhanced repair_clk_nets1.tcl for better test coverage

Signed-off-by: Jaehyun Kim <[email protected]>

Author: jhkim-pii

src/rsz/test/repair_clk_nets1.ok

@@ -4,10 +4,20 @@
 [INFO ODB-0131]     Created 3 components and 12 component-terminals.
 [INFO ODB-0132]     Created 2 special nets and 6 connections.
 [INFO ODB-0133]     Created 4 nets and 6 connections.
+
+# Set CLOCK type for all nets in the target path.
 [WARNING RSZ-0065] max wire length less than 693u increases wire delays.
 [INFO RSZ-0047] Found 1 long wires.
 [INFO RSZ-0048] Inserted 3 buffers in 1 nets.
-CLOCK
+
+# All nets in the path should be CLOCK type.
+in1: CLOCK
+n1: CLOCK
+n2: CLOCK
+net3: CLOCK
+net2: CLOCK
+net1: CLOCK
+out1: CLOCK
 Driver    length delay
 Startpoint: in1 (clock source 'in1')
 Endpoint: out1 (output port)
@@ -16,27 +26,66 @@ Path Type: max
 
     Cap    Slew   Delay    Time   Description
 -----------------------------------------------------------------------
-   0.97    0.00    0.00    0.00 ^ in1 (in)
+   1.02    0.00    0.00    0.00 ^ in1 (in)
            0.00    0.00    0.00 ^ u1/A (BUF_X1)
-   0.97    0.01    0.02    0.02 ^ u1/Z (BUF_X1)
+   1.01    0.01    0.02    0.02 ^ u1/Z (BUF_X1)
            0.01    0.00    0.02 ^ u2/A (BUF_X1)
-   6.59    0.02    0.03    0.05 ^ u2/Z (BUF_X1)
-           0.02    0.00    0.05 ^ wire3/A (BUF_X8)
-  42.96    0.01    0.03    0.08 ^ wire3/Z (BUF_X8)
-           0.04    0.03    0.11 ^ wire2/A (BUF_X16)
-  55.02    0.01    0.03    0.14 ^ wire2/Z (BUF_X16)
-           0.06    0.05    0.19 ^ wire1/A (BUF_X16)
-  43.61    0.01    0.03    0.22 ^ wire1/Z (BUF_X16)
-           0.04    0.03    0.25 ^ u3/A (BUF_X1)
-   0.00    0.01    0.02    0.27 ^ u3/Z (BUF_X1)
-           0.01    0.00    0.27 ^ out1 (out)
-                           0.27   data arrival time
+  40.52    0.08    0.10    0.11 ^ u2/Z (BUF_X1)
+           0.09    0.04    0.15 ^ wire3/A (BUF_X8)
+  42.96    0.01    0.03    0.18 ^ wire3/Z (BUF_X8)
+           0.04    0.03    0.22 ^ wire2/A (BUF_X16)
+  55.02    0.01    0.03    0.24 ^ wire2/Z (BUF_X16)
+           0.06    0.05    0.29 ^ wire1/A (BUF_X16)
+  43.61    0.01    0.03    0.32 ^ wire1/Z (BUF_X16)
+           0.04    0.03    0.36 ^ u3/A (BUF_X1)
+   0.10    0.01    0.03    0.38 ^ u3/Z (BUF_X1)
+           0.01    0.00    0.38 ^ out1 (out)
+                           0.38   data arrival time
 -----------------------------------------------------------------------
 (Path is unconstrained)
 
 
+
+# Check new buffer locations.
 Instance: u2, Location (unit: DBU): 0 0
 Instance: wire3, Location (unit: DBU): 902584 1383
 Instance: wire2, Location (unit: DBU): 1718366 1341
 Instance: wire1, Location (unit: DBU): 2858308 1283
 Instance: u3, Location (unit: DBU): 3998000 0
+
+# Call sta::network_changed. Timing should be the same.
+Startpoint: in1 (clock source 'in1')
+Endpoint: out1 (output port)
+Path Group: unconstrained
+Path Type: max
+
+    Cap    Slew   Delay    Time   Description
+-----------------------------------------------------------------------
+   1.02    0.00    0.00    0.00 ^ in1 (in)
+           0.00    0.00    0.00 ^ u1/A (BUF_X1)
+   1.01    0.01    0.02    0.02 ^ u1/Z (BUF_X1)
+           0.01    0.00    0.02 ^ u2/A (BUF_X1)
+  40.52    0.08    0.10    0.11 ^ u2/Z (BUF_X1)
+           0.09    0.04    0.15 ^ wire3/A (BUF_X8)
+  42.96    0.01    0.03    0.18 ^ wire3/Z (BUF_X8)
+           0.04    0.03    0.22 ^ wire2/A (BUF_X16)
+  55.02    0.01    0.03    0.24 ^ wire2/Z (BUF_X16)
+           0.06    0.05    0.29 ^ wire1/A (BUF_X16)
+  43.61    0.01    0.03    0.32 ^ wire1/Z (BUF_X16)
+           0.04    0.03    0.36 ^ u3/A (BUF_X1)
+   0.10    0.01    0.03    0.38 ^ u3/Z (BUF_X1)
+           0.01    0.00    0.38 ^ out1 (out)
+                           0.38   data arrival time
+-----------------------------------------------------------------------
+(Path is unconstrained)
+
+
+
+# All nets in the path should be CLOCK type after network_changed.
+in1: CLOCK
+n1: CLOCK
+n2: CLOCK
+net3: CLOCK
+net2: CLOCK
+net1: CLOCK
+out1: CLOCK

src/rsz/test/repair_clk_nets1.tcl

@@ -5,18 +5,31 @@ read_lef Nangate45/Nangate45.lef
 read_def repair_wire1.def
 create_clock in1 -period 10
 
+# If set_propagated_clock setting is omitted, `in1` is assumed to be
+# an ideal clock.
+# `estimate_parasitics -placement` does not compute RC for ideal clock nets.
+# Therefore, executing set_propagated_clock is crucial for calculating
+# an accurate RC.
+set_propagated_clock in1
+
 source Nangate45/Nangate45.rc
 set_wire_rc -layer metal3
 estimate_parasitics -placement
 
-foreach net_name {in1 n2 n2} {
+puts "\n# Set CLOCK type for all nets in the target path."
+foreach net_name {in1 n1 n2 out1} {
   [sta::sta_to_db_net [get_net $net_name]] setSigType CLOCK
 }
 
 # wire length = 1500u -> 2 buffers required
 repair_clock_nets -max_wire_length 600
 
-puts [[sta::sta_to_db_net [get_net net1]] getSigType]
+puts "\n# All nets in the path should be CLOCK type."
+foreach pin_name {u1/A u1/Z u2/Z wire3/Z wire2/Z wire1/Z u3/Z} {
+  set net [get_net -of_object [get_pins $pin_name]]
+  set net_name [get_name $net]
+  puts "$net_name: [[sta::sta_to_db_net $net] getSigType]"
+}
 
 report_long_wires 4
 report_checks -unconstrained -fields {input slew cap} -rise_to out1
@@ -26,8 +39,21 @@ proc location { inst_name args } {
   puts "Instance: $inst_name, Location (unit: DBU): [$inst getLocation]"
 }
 
+puts "\n# Check new buffer locations."
 location u2
 location wire3
 location wire2
 location wire1
 location u3
+
+puts "\n# Call sta::network_changed. Timing should be the same."
+sta::network_changed
+estimate_parasitics -placement
+report_checks -unconstrained -fields {input slew cap} -rise_to out1
+
+puts "\n# All nets in the path should be CLOCK type after network_changed."
+foreach pin_name {u1/A u1/Z u2/Z wire3/Z wire2/Z wire1/Z u3/Z} {
+  set net [get_net -of_object [get_pins $pin_name]]
+  set net_name [get_name $net]
+  puts "$net_name: [[sta::sta_to_db_net $net] getSigType]"
+}