dpl: update ok files

Signed-off-by: Eder Monteiro <[email protected]>

Author: eder-matheus

src/dpl/test/fillers2.defok

@@ -33,16 +33,14 @@ VIAS 3 ;
     - via5_960x2800 + VIARULE Via5Array-0 + CUTSIZE 280 280  + LAYERS metal5 metal6 via5  + CUTSPACING 320 320  + ENCLOSURE 40 60 40 60  + ROWCOL 5 2  ;
     - via6_960x2800 + VIARULE Via6Array-0 + CUTSIZE 280 280  + LAYERS metal6 metal7 via6  + CUTSPACING 320 320  + ENCLOSURE 340 360 340 360  + ROWCOL 4 1  ;
 END VIAS
-COMPONENTS 9 ;
-    - FILLER_0_0 FILLCELL_X2 + SOURCE DIST + PLACED ( 3800 2800 ) FS ;
-    - FILLER_0_25 FILLCELL_X4 + SOURCE DIST + PLACED ( 13300 2800 ) FS ;
-    - FILLER_0_29 FILLCELL_X2 + SOURCE DIST + PLACED ( 14820 2800 ) FS ;
+COMPONENTS 7 ;
+    - FILLER_0_23 FILLCELL_X8 + SOURCE DIST + PLACED ( 12540 2800 ) FS ;
     - FILLER_0_31 FILLCELL_X1 + SOURCE DIST + PLACED ( 15580 2800 ) FS ;
-    - FILLER_0_9 FILLCELL_X16 + SOURCE DIST + PLACED ( 7220 2800 ) FS ;
+    - FILLER_0_7 FILLCELL_X16 + SOURCE DIST + PLACED ( 6460 2800 ) FS ;
     - FILLER_1_0 FILLCELL_X32 + SOURCE DIST + PLACED ( 3800 5600 ) N ;
     - FILLER_2_0 FILLCELL_X32 + SOURCE DIST + PLACED ( 3800 8400 ) FS ;
     - FILLER_3_0 FILLCELL_X32 + SOURCE DIST + PLACED ( 3800 11200 ) N ;
-    - _277_ BUF_X4 + PLACED ( 4560 2800 ) FS ;
+    - _277_ BUF_X4 + PLACED ( 3800 2800 ) FS ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL

src/dpl/test/fillers2.ok

@@ -6,12 +6,12 @@
 [INFO ODB-0133]     Created 2 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          3.7 u
-average displacement        3.7 u
-max displacement            3.7 u
+total displacement          3.3 u
+average displacement        3.3 u
+max displacement            3.3 u
 original HPWL               2.3 u
-legalized HPWL              9.9 u
-delta HPWL                  332 %
+legalized HPWL              9.1 u
+delta HPWL                  299 %
 
-[INFO DPL-0001] Placed 8 filler instances.
+[INFO DPL-0001] Placed 6 filler instances.
 No differences found.

src/dpl/test/fillers2_verbose.ok

@@ -6,17 +6,16 @@
 [INFO ODB-0133]     Created 2 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          3.7 u
-average displacement        3.7 u
-max displacement            3.7 u
+total displacement          3.3 u
+average displacement        3.3 u
+max displacement            3.3 u
 original HPWL               2.3 u
-legalized HPWL              9.9 u
-delta HPWL                  332 %
+legalized HPWL              9.1 u
+delta HPWL                  299 %
 
-[INFO DPL-0001] Placed 8 filler instances.
+[INFO DPL-0001] Placed 6 filler instances.
 Filler usage:
   FILLCELL_X1:  1
   FILLCELL_X16: 1
-  FILLCELL_X2:  2
   FILLCELL_X32: 3
-  FILLCELL_X4:  1
+  FILLCELL_X8:  1

src/dpl/test/mirror2.def

@@ -35,7 +35,7 @@ VIAS 3 ;
 END VIAS
 COMPONENTS 2 ;
     - b1 BUF_X1 + PLACED ( 3800 2800 ) N ;
-    - block1 BLOCK1 + FIXED ( 4940 2810 ) N ;
+    - block1 BLOCK1 + FIXED ( 4560 2810 ) N ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL + FIXED ( 0 -140 ) N + LAYER metal6 ( -140 -140 ) ( 140 140 ) ;

src/dpl/test/mirror2.ok

@@ -8,12 +8,12 @@
 [INFO ODB-0133]     Created 3 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          2.9 u
-average displacement        1.4 u
-max displacement            2.9 u
-original HPWL               0.9 u
+total displacement          2.7 u
+average displacement        1.3 u
+max displacement            2.7 u
+original HPWL               0.7 u
 legalized HPWL              2.1 u
-delta HPWL                  136 %
+delta HPWL                  199 %
 
 block orient R0
 [INFO DPL-0020] Mirrored 1 instances

src/dpl/test/pad01.defok

@@ -34,7 +34,7 @@ VIAS 3 ;
     - via6_960x2800 + VIARULE Via6Array-0 + CUTSIZE 280 280  + LAYERS metal6 metal7 via6  + CUTSPACING 320 320  + ENCLOSURE 340 360 340 360  + ROWCOL 4 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - _277_ BUF_X4 + PLACED ( 5700 2800 ) FS ;
+    - _277_ BUF_X4 + PLACED ( 3800 2800 ) FS ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL

src/dpl/test/pad01.ok

@@ -6,11 +6,11 @@
 [INFO ODB-0133]     Created 2 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          4.2 u
-average displacement        4.2 u
-max displacement            4.2 u
+total displacement          3.3 u
+average displacement        3.3 u
+max displacement            3.3 u
 original HPWL               2.3 u
-legalized HPWL             11.0 u
-delta HPWL                  382 %
+legalized HPWL              9.1 u
+delta HPWL                  299 %
 
 No differences found.

src/dpl/test/pad07.defok

@@ -34,7 +34,7 @@ VIAS 3 ;
     - via6_960x2800 + VIARULE Via6Array-0 + CUTSIZE 280 280  + LAYERS metal6 metal7 via6  + CUTSPACING 320 320  + ENCLOSURE 340 360 340 360  + ROWCOL 4 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - _277_ BUF_X4 + PLACED ( 5700 2800 ) FS ;
+    - _277_ BUF_X4 + PLACED ( 3800 2800 ) FS ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL

src/dpl/test/pad07.ok

@@ -6,11 +6,11 @@
 [INFO ODB-0133]     Created 2 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          4.2 u
-average displacement        4.2 u
-max displacement            4.2 u
+total displacement          3.3 u
+average displacement        3.3 u
+max displacement            3.3 u
 original HPWL               2.3 u
-legalized HPWL             11.0 u
-delta HPWL                  382 %
+legalized HPWL              9.1 u
+delta HPWL                  299 %
 
 No differences found.

src/dpl/test/pad08.defok

@@ -34,7 +34,7 @@ VIAS 3 ;
     - via6_960x2800 + VIARULE Via6Array-0 + CUTSIZE 280 280  + LAYERS metal6 metal7 via6  + CUTSPACING 320 320  + ENCLOSURE 340 360 340 360  + ROWCOL 4 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - _277_ BUF_X4 + PLACED ( 5700 2800 ) FS ;
+    - _277_ BUF_X4 + PLACED ( 3800 2800 ) FS ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL