Merge pull request #275 from The-OpenROAD-Project/dbSta_find_clks

dbSta::findClkNets

Author: jjcherry56

src/dbSta/include/db_sta/dbSta.hh

@@ -54,6 +54,9 @@ public:
   virtual void postReadDef(odb::dbBlock* block) override;
   virtual void postReadDb(odb::dbDatabase* db) override;
 
+  // Find clock nets connected by combinational gates from the clock roots. 
+  void findClkNets(std::set<dbNet*> &clk_nets);
+
 protected:
   virtual void makeNetwork() override;
   virtual void makeSdcNetwork() override;

src/dbSta/src/CMakeLists.txt

@@ -53,7 +53,7 @@ add_custom_command(OUTPUT ${DBSTA_TCL_INIT}
   )
 
 add_custom_command(OUTPUT ${DBSTA_WRAP}
-  COMMAND ${SWIG_EXECUTABLE} -tcl8 -c++ -namespace -prefix sta -I${OPENSTA_HOME} -o ${DBSTA_WRAP} ${DBSTA_HOME}/src/dbSta.i
+  COMMAND ${SWIG_EXECUTABLE} -tcl8 -c++ -namespace -prefix sta -I${OPENSTA_HOME} -I${OPENDB_HOME}/src/swig/tcl -o ${DBSTA_WRAP} ${DBSTA_HOME}/src/dbSta.i
   COMMAND ${OPENSTA_HOME}/etc/SwigCleanup.tcl ${DBSTA_WRAP}
   WORKING_DIRECTORY ${OPENROAD_HOME}/src/dbSta
   DEPENDS ${DBSTA_SWIG_FILES}

src/dbSta/src/dbSta.cc

@@ -19,6 +19,9 @@
 #include <tcl.h>
 
 #include "sta/StaMain.hh"
+#include "sta/Graph.hh"
+#include "sta/Search.hh"
+#include "sta/Bfs.hh"
 #include "db_sta/dbNetwork.hh"
 #include "db_sta/MakeDbSta.hh"
 #include "opendb/db.h"
@@ -152,5 +155,32 @@ dbSta::netSlack(const dbNet *db_net,
   return netSlack(net, min_max);
 }
 
+void
+dbSta::findClkNets(std::set<dbNet*> &clk_nets)
+{
+  ensureGraph();
+  ensureLevelized();
+  ClkArrivalSearchPred srch_pred(this);
+  BfsFwdIterator bfs(BfsIndex::other, &srch_pred, this);
+  PinSet clk_pins;
+  search_->findClkVertexPins(clk_pins);
+  for (Pin *pin : clk_pins) {
+    Vertex *vertex, *bidirect_drvr_vertex;
+    graph_->pinVertices(pin, vertex, bidirect_drvr_vertex);
+    bfs.enqueue(vertex);
+    if (bidirect_drvr_vertex)
+      bfs.enqueue(bidirect_drvr_vertex);
+  }  
+  while (bfs.hasNext()) {
+    Vertex *vertex = bfs.next();
+    const Pin *pin = vertex->pin();
+    if (!network_->isTopLevelPort(pin)) {
+      Net *net = network_->net(pin);
+      clk_nets.insert(db_network_->staToDb(net));
+    }
+    bfs.enqueueAdjacentVertices(vertex);
+  }
+}
+
 } // namespace sta
 

src/dbSta/src/dbSta.i

@@ -32,6 +32,18 @@ make_block_sta(odb::dbBlock *block)
   return sta::makeBlockSta(block);
 }
 
+// For debugging because I can't get a dbNet vector thru swig.
+void
+report_clk_nets()
+{
+  ord::OpenRoad *openroad = ord::getOpenRoad();
+  sta::dbSta *sta = openroad->getSta();
+  std::set<dbNet*> clk_nets;
+  sta->findClkNets(clk_nets);
+  for (dbNet *net : clk_nets)
+    printf("%s\n", net->getConstName());
+}
+
 odb::dbInst *
 sta_to_db_inst(Instance *inst)
 {

src/dbSta/test/Nangate45

@@ -0,0 +1 @@
+../../../test/Nangate45

src/dbSta/test/bus1.def

@@ -1,4 +1,4 @@
-VERSION 5.5 ;
+VERSION 5.8 ;
 NAMESCASESENSITIVE ON ;
 DIVIDERCHAR "/" ;
 BUSBITCHARS "[]" ;

src/dbSta/test/find_clks1.def

@@ -0,0 +1,41 @@
+VERSION 5.8 ; 
+NAMESCASESENSITIVE ON ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+
+DESIGN top ;
+
+UNITS DISTANCE MICRONS 1000 ;
+
+DIEAREA ( 0 0 ) ( 1000 1000 ) ;
+
+COMPONENTS 5 ;
+- r1 DFF_X1 ;
+- r2 DFF_X1 ;
+- u1 BUF_X1 ;
+- p1 PAD ;
+END COMPONENTS
+
+PINS 6 ;
+- in1 + NET in1 + DIRECTION INPUT ;
+- clk1 + NET clk1 + DIRECTION INPUT ;
+- out1 + NET out + DIRECTION OUTPUT ;
+END PINS
+
+SPECIALNETS 2 ;
+- VSS  ( * VSS )
+  + USE GROUND ;
+- VDD  ( * VDD )
+  + USE POWER ;
+END SPECIALNETS
+
+NETS 10 ;
+- in1 ( PIN in1 ) ( r1 D ) ;
+- clk1 ( PIN clk1 ) ( p1 PAD ) ;
+- clk2 ( p1 Y ) ( r1 CK ) ( r2 CK ) ;
+- r1q ( r1 Q ) ( u1 A ) ;
+- u1z ( u1 Z ) ( r2 D ) ;
+- out1 ( r2 Q ) ( PIN out1 ) ;
+END NETS
+
+END DESIGN

src/dbSta/test/find_clks1.ok

@@ -0,0 +1,19 @@
+Notice 0: Reading LEF file:  Nangate45/Nangate45.lef
+Notice 0:     Created 22 technology layers
+Notice 0:     Created 27 technology vias
+Notice 0:     Created 134 library cells
+Notice 0: Finished LEF file:  Nangate45/Nangate45.lef
+Notice 0: Reading LEF file:  pad.lef
+Notice 0: error: undefined layer (C4) referenced
+Notice 0:     Created 1 library cells
+Notice 0: Finished LEF file:  pad.lef
+Notice 0: 
+Reading DEF file: find_clks1.def
+Notice 0: Design: top
+Notice 0:     Created 3 pins.
+Notice 0:     Created 4 components and 23 component-terminals.
+Notice 0:     Created 2 special nets and 6 connections.
+Notice 0:     Created 6 nets and 10 connections.
+Notice 0: Finished DEF file: find_clks1.def
+clk1
+clk2

src/dbSta/test/find_clks1.tcl

@@ -0,0 +1,9 @@
+# find_clks from input port thru pad
+read_lef Nangate45/Nangate45.lef
+read_lef pad.lef
+read_liberty Nangate45/Nangate45_typ.lib
+read_liberty pad.lib
+read_def find_clks1.def
+
+create_clock -name clk -period 10 clk1
+sta::report_clk_nets

src/dbSta/test/pad.lef

@@ -0,0 +1,49 @@
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+SITE IO_SITE
+  CLASS PAD ;
+  SIZE 1 BY 150 ;
+END IO_SITE
+
+MACRO PAD
+  CLASS PAD ;
+  ORIGIN 0 0 ;
+  SIZE 25 BY 100 ;
+  SYMMETRY X Y ;
+  SITE IO_SITE ;
+  PIN PAD
+    DIRECTION INOUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER C4 ;
+        RECT 1.15 0 28.85 0.5 ;
+    END
+  END PAD
+  PIN NDOUT
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+  END NDOUT
+  PIN Y
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+  END Y
+  PIN TRIEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+  END TRIEN
+  PIN RXEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+  END RXEN
+  PIN DATA
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+  END DATA
+  PIN NDIN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+  END NDIN
+END PAD
+