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TheMightyDuckOfDoomTheMightyDuckOfDoom
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rmp: Resynthesis: Fix memory macros, set_dont_use and set_dont_touch
Signed-off-by: Tobias Senti <[email protected]>
1 parent f470d08 commit 6bb2ac5

19 files changed

+597
-10
lines changed

‎src/rmp/src/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ target_link_libraries(rmp_abc_library
6666
OpenSTA
6767
dbSta_lib
6868
utl_lib
69+
rsz_lib
6970
${ABC_LIBRARY}
7071
)
7172

‎src/rmp/src/Restructure.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,8 @@ void Restructure::reset()
7474
void Restructure::resynth(sta::Corner* corner)
7575
{
7676
ZeroSlackStrategy zero_slack_strategy(corner);
77-
zero_slack_strategy.OptimizeDesign(open_sta_, name_generator_, logger_);
77+
zero_slack_strategy.OptimizeDesign(
78+
open_sta_, name_generator_, resizer_, logger_);
7879
}
7980

8081
void Restructure::run(char* liberty_file_name,

‎src/rmp/src/abc_library_factory.cpp‎

Lines changed: 20 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ static bool IsCombinational(sta::LibertyCell* cell)
4141
}
4242
return (!cell->isClockGate() && !cell->isPad() && !cell->isMacro()
4343
&& !cell->hasSequentials() && !cell->isLevelShifter()
44-
&& !cell->isIsolationCell() && !cell->isClockGate());
44+
&& !cell->isIsolationCell() && !cell->isMemory());
4545
}
4646

4747
static int CountOutputPins(sta::LibertyCell* cell)
@@ -76,8 +76,12 @@ static bool HasNonInputOutputPorts(sta::LibertyCell* cell)
7676
return false;
7777
}
7878

79-
static bool isCompatibleWithAbc(sta::LibertyCell* cell)
79+
static bool isCompatibleWithAbc(sta::LibertyCell* cell, rsz::Resizer* resizer)
8080
{
81+
if (resizer != nullptr && resizer->dontUse(cell)) {
82+
return false;
83+
}
84+
8185
if (!IsCombinational(cell)) {
8286
return false;
8387
}
@@ -213,6 +217,13 @@ std::vector<abc::SC_Pin*> AbcLibraryFactory::CreateAbcOutputPins(
213217
output_pin->max_out_slew = time_unit->staToUser(max_output_slew);
214218
}
215219

220+
if (cell_port->function() == nullptr) {
221+
logger_->error(utl::RMP,
222+
27,
223+
"cell port function is null for cell {}:{}",
224+
cell->name(),
225+
cell_port->name());
226+
}
216227
output_pin->func_text = strdup(cell_port->function()->to_string().c_str());
217228

218229
// Get list of input ports
@@ -312,6 +323,12 @@ AbcLibraryFactory& AbcLibraryFactory::AddDbSta(sta::dbSta* db_sta)
312323
return *this;
313324
}
314325

326+
AbcLibraryFactory& AbcLibraryFactory::AddResizer(rsz::Resizer* resizer)
327+
{
328+
resizer_ = resizer;
329+
return *this;
330+
}
331+
315332
AbcLibraryFactory& AbcLibraryFactory::SetCorner(sta::Corner* corner)
316333
{
317334
corner_ = corner;
@@ -418,7 +435,7 @@ void AbcLibraryFactory::PopulateAbcSclLibFromSta(
418435
// Loop through all of the cells in STA and create equivalents in
419436
// the ABC structure.
420437
for (sta::LibertyCell* cell : cells) {
421-
if (!isCompatibleWithAbc(cell)) {
438+
if (!isCompatibleWithAbc(cell, resizer_)) {
422439
continue;
423440
}
424441

‎src/rmp/src/abc_library_factory.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212

1313
#include "db_sta/dbSta.hh"
1414
#include "map/scl/sclLib.h"
15+
#include "rsz/Resizer.hh"
1516
#include "sta/Sta.hh"
1617
#include "utl/Logger.h"
1718
#include "utl/deleter.h"
@@ -54,6 +55,7 @@ class AbcLibraryFactory
5455
public:
5556
explicit AbcLibraryFactory(utl::Logger* logger) : logger_(logger) {}
5657
AbcLibraryFactory& AddDbSta(sta::dbSta* db_sta);
58+
AbcLibraryFactory& AddResizer(rsz::Resizer* resizer);
5759
AbcLibraryFactory& SetCorner(sta::Corner* corner);
5860
AbcLibrary Build();
5961

@@ -78,6 +80,7 @@ class AbcLibraryFactory
7880
utl::Logger* logger_;
7981
sta::dbSta* db_sta_ = nullptr;
8082
sta::Corner* corner_ = nullptr;
83+
rsz::Resizer* resizer_ = nullptr;
8184
};
8285

8386
} // namespace rmp

‎src/rmp/src/resynthesis_strategy.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55

66
#include "db_sta/dbSta.hh"
77
#include "rmp/unique_name.h"
8+
#include "rsz/Resizer.hh"
89
#include "utl/Logger.h"
910

1011
namespace rmp {
@@ -15,6 +16,7 @@ class ResynthesisStrategy
1516
virtual ~ResynthesisStrategy() = default;
1617
virtual void OptimizeDesign(sta::dbSta* sta,
1718
rmp::UniqueName& name_generator,
19+
rsz::Resizer* resizer,
1820
utl::Logger* logger)
1921
= 0;
2022
};

‎src/rmp/src/zero_slack_strategy.cpp‎

Lines changed: 24 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -24,17 +24,26 @@
2424

2525
namespace rmp {
2626

27-
std::vector<sta::Vertex*> GetNegativeEndpoints(sta::dbSta* sta)
27+
std::vector<sta::Vertex*> GetNegativeEndpoints(sta::dbSta* sta,
28+
rsz::Resizer* resizer)
2829
{
2930
std::vector<sta::Vertex*> result;
3031

3132
sta::dbNetwork* network = sta->getDbNetwork();
3233
for (sta::Vertex* vertex : *sta->endpoints()) {
33-
sta::PortDirection* direction = network->direction(vertex->pin());
34+
sta::Pin* pin = vertex->pin();
35+
sta::PortDirection* direction = network->direction(pin);
3436
if (!direction->isInput()) {
3537
continue;
3638
}
3739

40+
if (resizer != nullptr) {
41+
if (resizer->dontTouch(pin) || resizer->dontTouch(network->net(pin))
42+
|| resizer->dontTouch(network->instance(pin))) {
43+
continue;
44+
}
45+
}
46+
3847
const sta::Slack slack = sta->vertexSlack(vertex, sta::MinMax::max());
3948

4049
if (slack > 0.0) {
@@ -48,6 +57,7 @@ std::vector<sta::Vertex*> GetNegativeEndpoints(sta::dbSta* sta)
4857

4958
void ZeroSlackStrategy::OptimizeDesign(sta::dbSta* sta,
5059
UniqueName& name_generator,
60+
rsz::Resizer* resizer,
5161
utl::Logger* logger)
5262
{
5363
sta->ensureGraph();
@@ -57,16 +67,19 @@ void ZeroSlackStrategy::OptimizeDesign(sta::dbSta* sta,
5767

5868
sta::dbNetwork* network = sta->getDbNetwork();
5969

60-
std::vector<sta::Vertex*> candidate_vertices = GetNegativeEndpoints(sta);
70+
std::vector<sta::Vertex*> candidate_vertices
71+
= GetNegativeEndpoints(sta, resizer);
6172

6273
if (candidate_vertices.empty()) {
63-
logger->info(
64-
utl::RMP, 1030, "All endpoints have positive slack, nothing to do.");
74+
logger->info(utl::RMP,
75+
1030,
76+
"All candidate endpoints have positive slack, nothing to do.");
6577
return;
6678
}
6779

6880
AbcLibraryFactory factory(logger);
6981
factory.AddDbSta(sta);
82+
factory.AddResizer(resizer);
7083
factory.SetCorner(corner_);
7184
AbcLibrary abc_library = factory.Build();
7285

@@ -82,6 +95,12 @@ void ZeroSlackStrategy::OptimizeDesign(sta::dbSta* sta,
8295

8396
LogicCut cut = logic_extractor.BuildLogicCut(abc_library);
8497

98+
if (cut.IsEmpty()) {
99+
logger->warn(
100+
utl::RMP, 1032, "Logic cut is empty after extraction, nothing to do.");
101+
return;
102+
}
103+
85104
utl::UniquePtrWithDeleter<abc::Abc_Ntk_t> mapped_abc_network
86105
= cut.BuildMappedAbcNetwork(abc_library, network, logger);
87106

‎src/rmp/src/zero_slack_strategy.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#include "db_sta/dbSta.hh"
77
#include "resynthesis_strategy.h"
88
#include "rmp/unique_name.h"
9+
#include "rsz/Resizer.hh"
910
#include "sta/Corner.hh"
1011
#include "utl/Logger.h"
1112

@@ -17,6 +18,7 @@ class ZeroSlackStrategy : public ResynthesisStrategy
1718
explicit ZeroSlackStrategy(sta::Corner* corner = nullptr) : corner_(corner) {}
1819
void OptimizeDesign(sta::dbSta* sta,
1920
UniqueName& name_generator,
21+
rsz::Resizer* resizer,
2022
utl::Logger* logger) override;
2123

2224
private:

‎src/rmp/test/BUILD‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,9 @@ COMPULSORY_TESTS = [
1717
"gcd_restructure",
1818
"aes_asap7",
1919
"gcd_asap7",
20+
"memory_nangate45",
21+
"aes_dontuse_nangate45",
22+
"aes_donttouch_nangate45"
2023
]
2124

2225
# Disabled in CMakeLists.txt

‎src/rmp/test/CMakeLists.txt‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,9 @@ or_integration_tests(
1414
gcd_restructure
1515
aes_asap7
1616
gcd_asap7
17+
memory_nangate45
18+
aes_dontuse_nangate45
19+
aes_donttouch_nangate45
1720
)
1821

1922
# Skipped

‎src/rmp/test/aes_donttouch_nangate45.ok‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,126 @@
1+
[INFO ODB-0227] LEF file: ./Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
2+
[INFO ODB-0227] LEF file: ./Nangate45/Nangate45_stdcell.lef, created 135 library cells
3+
[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.
4+
-- Before --
5+
6+
Cell type report: Count Area
7+
Buffer 1908 2138.64
8+
Inverter 225 139.92
9+
Sequential cell 530 2396.66
10+
Multi-Input combinational cell 14095 17315.54
11+
Total 16758 21990.75
12+
[-0.369, -0.296): ********************************************** (127)
13+
[-0.296, -0.223): ************************* (69)
14+
[-0.223, -0.150): ********************* (57)
15+
[-0.150, -0.076): ********************************************** (129)
16+
[-0.076, -0.003): * (2)
17+
[-0.003, 0.070): (0)
18+
[ 0.070, 0.143): * (2)
19+
[ 0.143, 0.217): ************************************************** (139)
20+
[ 0.217, 0.290): * (4)
21+
[ 0.290, 0.363]: *********************************************** (130)
22+
Startpoint: _33243_ (rising edge-triggered flip-flop clocked by core_clock)
23+
Endpoint: _33122_ (rising edge-triggered flip-flop clocked by core_clock)
24+
Path Group: core_clock
25+
Path Type: max
26+
27+
Delay Time Description
28+
---------------------------------------------------------
29+
0.00 0.00 clock core_clock (rise edge)
30+
0.00 0.00 clock network delay (ideal)
31+
0.00 0.00 ^ _33243_/CK (DFF_X1)
32+
0.09 0.09 ^ _33243_/Q (DFF_X1)
33+
0.03 0.12 ^ _29829_/Z (BUF_X2)
34+
0.03 0.15 ^ _29921_/ZN (OR2_X1)
35+
0.03 0.18 ^ _29922_/Z (BUF_X4)
36+
0.02 0.20 v _29923_/ZN (NOR3_X2)
37+
0.09 0.28 ^ _30031_/ZN (AOI222_X2)
38+
0.04 0.33 v _30041_/ZN (OAI221_X1)
39+
0.08 0.41 v _32345_/ZN (OR4_X2)
40+
0.08 0.49 ^ _32346_/ZN (NOR4_X2)
41+
0.05 0.54 v _32347_/ZN (NAND4_X2)
42+
0.07 0.61 v _32588_/Z (XOR2_X2)
43+
0.06 0.67 v _32661_/Z (XOR2_X1)
44+
0.04 0.71 v _32662_/ZN (XNOR2_X1)
45+
0.06 0.77 v _32663_/Z (MUX2_X1)
46+
0.05 0.83 v _32664_/Z (XOR2_X1)
47+
0.00 0.83 v _33122_/D (DFF_X1)
48+
0.83 data arrival time
49+
50+
0.50 0.50 clock core_clock (rise edge)
51+
0.00 0.50 clock network delay (ideal)
52+
0.00 0.50 clock reconvergence pessimism
53+
0.50 ^ _33122_/CK (DFF_X1)
54+
-0.04 0.46 library setup time
55+
0.46 data required time
56+
---------------------------------------------------------
57+
0.46 data required time
58+
-0.83 data arrival time
59+
---------------------------------------------------------
60+
-0.37 slack (VIOLATED)
61+
62+
63+
wns max -0.37
64+
tns max -83.81
65+
-- After --
66+
67+
[INFO RMP-1030] All candidate endpoints have positive slack, nothing to do.
68+
[-0.369, -0.296): ********************************************** (127)
69+
[-0.296, -0.223): ************************* (69)
70+
[-0.223, -0.150): ********************* (57)
71+
[-0.150, -0.076): ********************************************** (129)
72+
[-0.076, -0.003): * (2)
73+
[-0.003, 0.070): (0)
74+
[ 0.070, 0.143): * (2)
75+
[ 0.143, 0.217): ************************************************** (139)
76+
[ 0.217, 0.290): * (4)
77+
[ 0.290, 0.363]: *********************************************** (130)
78+
Cell type report: Count Area
79+
Buffer 1908 2138.64
80+
Inverter 225 139.92
81+
Sequential cell 530 2396.66
82+
Multi-Input combinational cell 14095 17315.54
83+
Total 16758 21990.75
84+
Startpoint: _33243_ (rising edge-triggered flip-flop clocked by core_clock)
85+
Endpoint: _33122_ (rising edge-triggered flip-flop clocked by core_clock)
86+
Path Group: core_clock
87+
Path Type: max
88+
89+
Delay Time Description
90+
---------------------------------------------------------
91+
0.00 0.00 clock core_clock (rise edge)
92+
0.00 0.00 clock network delay (ideal)
93+
0.00 0.00 ^ _33243_/CK (DFF_X1)
94+
0.09 0.09 ^ _33243_/Q (DFF_X1)
95+
0.03 0.12 ^ _29829_/Z (BUF_X2)
96+
0.03 0.15 ^ _29921_/ZN (OR2_X1)
97+
0.03 0.18 ^ _29922_/Z (BUF_X4)
98+
0.02 0.20 v _29923_/ZN (NOR3_X2)
99+
0.09 0.28 ^ _30031_/ZN (AOI222_X2)
100+
0.04 0.33 v _30041_/ZN (OAI221_X1)
101+
0.08 0.41 v _32345_/ZN (OR4_X2)
102+
0.08 0.49 ^ _32346_/ZN (NOR4_X2)
103+
0.05 0.54 v _32347_/ZN (NAND4_X2)
104+
0.07 0.61 v _32588_/Z (XOR2_X2)
105+
0.06 0.67 v _32661_/Z (XOR2_X1)
106+
0.04 0.71 v _32662_/ZN (XNOR2_X1)
107+
0.06 0.77 v _32663_/Z (MUX2_X1)
108+
0.05 0.83 v _32664_/Z (XOR2_X1)
109+
0.00 0.83 v _33122_/D (DFF_X1)
110+
0.83 data arrival time
111+
112+
0.50 0.50 clock core_clock (rise edge)
113+
0.00 0.50 clock network delay (ideal)
114+
0.00 0.50 clock reconvergence pessimism
115+
0.50 ^ _33122_/CK (DFF_X1)
116+
-0.04 0.46 library setup time
117+
0.46 data required time
118+
---------------------------------------------------------
119+
0.46 data required time
120+
-0.83 data arrival time
121+
---------------------------------------------------------
122+
-0.37 slack (VIOLATED)
123+
124+
125+
wns max -0.37
126+
tns max -83.81

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