par: fix sdc in write_artnet test

maliberty · maliberty · commit 6ffc9e3a7a7e · 2025-09-16T05:46:17.000Z
Signed-off-by: Matt Liberty &lt;mliberty@precisioninno.com&gt;
diff --git a/src/par/test/write_artnet.ok b/src/par/test/write_artnet.ok
@@ -1,4 +1,5 @@
 [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.
 getFromODB done
 getFromSTA done
 getFromPAR done
diff --git a/src/par/test/write_artnet.tcl b/src/par/test/write_artnet.tcl
@@ -1,12 +1,13 @@
 source "helpers.tcl"
+source flow_helpers.tcl
 
 read_liberty "Nangate45/Nangate45_typ.lib"
 read_lef Nangate45/Nangate45.lef
 
 read_verilog gcd.v
 link_design gcd
 
-read_sdc gcd.sdc
+read_sdc gcd_nangate45.sdc
 
 set spec_file [make_result_file  write_artnet.spec]
 write_artnet_spec -out_file $spec_file

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,5 @@`
`1`	`1`	`[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells`
	`2`	`+[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.`
`2`	`3`	`getFromODB done`
`3`	`4`	`getFromSTA done`
`4`	`5`	`getFromPAR done`